CMOS Spiking Neuron Circuit for Analog ReRAM Synapse Arrays
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Solution Overview
Problem
Existing spiking neural networks (SNNs) face challenges in achieving high accuracy and energy efficiency due to limited understanding of biological neural systems, limited endurance of emerging memory devices, and inefficiencies in digital hardware implementations, leading to restricted practical utility and increased energy consumption.
Innovation Solution
An all-analog hardware SNN is developed using ReRAM-crossbar synapse arrays and custom-designed CMOS spike response model (SRM) neuron circuits, achieving 97.78% accuracy on the N-MNIST dataset with low latency and high energy efficiency, leveraging a software-hardware codesign approach and linear temporal dynamics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If SNNs are implemented on digital hardware (CPUs, GPUs, FPGAs), then information processing can be performed, but energy consumption increases significantly due to translation overhead to digital representations
Solution Approach 1:
The patent replaces digital mechanical computation systems with analog electronic systems that directly emulate biological neural behavior. The analog neuromorphic system uses continuous voltage signals to represent membrane potentials and current signals to represent synaptic inputs, eliminating the need for digital-to-analog conversion and significantly reducing energy consumption while maintaining computational functionality.
Solution Approach 2:
The patent changes the fundamental operating parameters from digital discrete levels to analog continuous values. By using continuous voltage ranges to represent neural states and implementing synaptic weights as analog conductance values, the system achieves native analog computation that matches biological neural processing characteristics, thereby reducing translation overhead and energy usage.
2Use of energy by moving object
If emerging memory devices (ReRAM, memristors) are used to implement neuromorphic systems, then energy efficiency improves, but accuracy falls short due to limited understanding of biological neural systems
Solution Approach 1:
The patent introduces operational amplifier-based integrator circuits as intermediary components between the emerging memory devices and the output. These integrators accurately accumulate synaptic inputs over time according to the leaky integrate-and-fire model, compensating for device variations and non-idealities in ReRAM/memristor devices, thereby achieving high accuracy while maintaining the energy efficiency benefits of emerging memories.
Solution Approach 2:
The patent implements feedback mechanisms through the integrator circuits that continuously monitor and adjust the membrane potential based on accumulated synaptic inputs. This feedback control compensates for device variability and non-linearities in emerging memory devices, enabling accurate spike timing and threshold detection despite the inherent limitations of the memory devices.
3Use of energy by moving object
If MOSFETs operate in subthreshold domain to achieve ultra-low power, then energy consumption decreases, but operational speed is restricted to millisecond time scale
Solution Approach 1:
The patent employs dynamic operation modes where MOSFETs can switch between subthreshold and saturation regions depending on the operational phase. During integration phases, devices operate in subthreshold for low power, while during spike generation and transmission phases, they transition to saturation mode to achieve fast switching and high-speed operation, thereby resolving the speed-power tradeoff.
Solution Approach 2:
The patent uses periodic spiking operation where neurons remain in low-power subthreshold mode during integration periods and briefly transition to high-speed saturation mode for spike generation. This periodic switching between operational modes allows the system to achieve ultra-low average power consumption while maintaining the capability for fast neural communication when needed.
4Loss of time
If analog neuron circuits are designed for high speed operation, then latency decreases, but circuit complexity increases due to additional control circuits
Solution Approach 1:
The patent extracts and separates the control functions into dedicated simple circuits. The spike generation control is implemented through a separate comparator circuit that independently monitors the membrane potential, while the reset control is handled by a dedicated switch controlled by the spike output. This separation of control functions reduces the complexity burden on the main integrator circuit and enables high-speed operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SNN hardware achieves significantly higher accuracy and lower latency compared to existing SNN implementations, with an inter-spike interval of 94.75 ps and energy consumption of 1.16 pJ per spike, outperforming digital hardware by several orders of magnitude in terms of energy efficiency and inference time.
Implementation Method 1
ReRAM-crossbar synapse arrays
Implementation Method 2
analog memory-based synaptic array
Implementation Method 3
custom-designed CMOS spike response model (SRM) neuron circuits
Implementation Method 4
linear temporal dynamics
Implementation Method 5
an operational amplifier, which receives a pair of input currents and outputs a signal corresponding to a difference between the input currents
Data Source
AI summary
An all-analog spiking neural network circuit including at least one ReRAM-crossbar synapse array that conducts multiply-accumulate operations in parallel and a spike response model (SRM) neuron circuit, which is built with complementary metal-oxide-semiconductor (CMOS) technology. The neuron circuits receive outputs from the ReRAM-crossbar synapse array and directly process the output currents from the ReRAM-crossbar synapse arrays to complete the multiply-accumulate operation and produce processed voltage spike trains.