CMOS Switch Capacitor Isolation for Low Leakage
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Solution Overview
Problem
In low-power applications, DC-DC converters face challenges in minimizing power consumption due to high leakage currents in isolating FET switches, especially at high temperatures, which affects the accuracy and efficiency of reference voltage generation.
Innovation Solution
Incorporating an additional smaller storage capacitor in parallel with the main capacitor to reduce sub-threshold leakage, and using a dual-switch configuration to manage leakage currents, allowing the reference generation circuit to be activated less frequently and reducing average power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the storage capacitor size is increased to reduce sub-threshold leakage, then leakage reduction is achieved, but chip area increases significantly
Solution Approach 1:
The patent divides the single large storage capacitor into two smaller capacitors (first storage capacitor and second storage capacitor) connected in parallel. This segmentation achieves equivalent or superior leakage reduction performance while occupying less total chip area, as the combined area of two smaller capacitors is less than one large capacitor of equivalent capacity.
2Use of energy by moving object
If the isolating FET switch is used to isolate the capacitor, then power consumption is reduced, but leakage current increases at high temperatures
Solution Approach 1:
The patent introduces a second isolating FET switch as an intermediary component between the first isolating FET switch and the first storage capacitor. This dual-switch configuration creates additional isolation pathways that reduce leakage current at high temperatures while maintaining low power consumption, as the distributed switching architecture reduces the burden on any single switch.
3Measurement precision
If the reference generation circuit is activated frequently to maintain accuracy, then reference voltage accuracy is improved, but average power consumption increases
Solution Approach 1:
The patent enables the reference generation circuit to be activated periodically rather than continuously, using the dual-capacitor and dual-switch architecture to maintain reference voltage accuracy during idle periods. The first and second storage capacitors work together to preserve voltage accuracy while allowing the circuit to enter low-power states, significantly reducing average power consumption while maintaining the required level of precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly extends the time the reference voltage is maintained with minimal power consumption, achieving a five-fold improvement in hold time while minimizing the increase in chip area, thus optimizing power management in low-power devices.
Implementation Method 1
reduce the sub-threshold leakage of an isolating FET switches at high temperatures
Data Source
AI summary
One or more embodiments enable both a fixed bandgap reference voltage and a variable reference voltage to be generated and stored on a capacitor. According to certain aspects, the present embodiments use an additional storage capacitor of smaller size to reduce the sub-threshold leakage of an isolating FET switches at high temperatures. Among other aspects, this enables a more efficient use of chip area for reducing sub-threshold induced leakage than simply increasing the storage capacitor when precision storage is required.