Segmented converter valve elements on post-like insulation reduce equipment bulkiness and development costs for HVDC systems.
Segmented charge pump and buck stages reduce output ripple while maintaining rapid transient response without post-regulators.
A buck-boost latch circuitry stabilizes switching frequency in step-up-step-down converters using predetermined on-time values.
A charge extraction circuit actively removes excess energy from output capacitors to stabilize voltage levels during operation.
Asymmetric transconductance multiphase DCDC converter balances load sharing to maintain high efficiency at low and medium loads.
A smart snubber circuit uses a switching device to dynamically connect or disconnect from voltage regulator circuitry.
A multilevel converter uses a flying capacitor to limit voltage across transistors during surges.
A saturation controller measures primary stroke lengths to adjust switching periods in flyback power supplies.
A switching power source device disables automatic dead time adjustment when no coil voltage is detected, preventing simultaneous turn-on of switching elements.
A voltage regulator generates current pulses in discontinuous mode to maintain stable output voltage during load changes.
A DC-DC power converter controller manages dynamic transitions between voltage and current modes using switched inductance circuits.
A multi-phase DC/DC converter adjusts switch timings to maintain current balance across parallel output circuits.
A power converter modifies its current sense signal using output voltage feedback to adjust the current limit dynamically.
A signal transmission device converts data formats between incompatible camera and circuit board interfaces.
Output selection circuit monitors voltage levels to generate control signals for switching current paths through a shared reactor.
Estimating output inductor inductance via switch node voltage comparison eliminates manual compensation adjustments and prevents system shutdowns.
Segmented casing vents direct airflow to cool densely packed circuit boards while preventing dust ingress that causes short circuits.
A power supply adjusts voltage via a comparator and current-to-voltage transform circuit to stabilize output.
A regulating power converter retrieves time information from secondary voltage to drive transformer discharge for output regulation.
Calculated LC segments simulate transmission lines, reducing component count and cross-talk in high-frequency converters.
A controller generates a half signal to sample switching current at its falling edge for precise regulation.
A PWM controller integrates over-temperature protection using a thermal resistor to adjust the driving signal voltage during off-periods.
A multi-slope startup voltage regulator system measures output voltage slopes to dynamically adjust its transfer function during power-up.
A switched capacitor circuit simulates large capacitance to filter sense voltage signals in power converters.
Rectifying and charge storage elements mitigate parasitic voltage ringing and overshoot at output terminals during switching operations.
A pulse width modulated controller system uses a calibration unit with comparators and encoder logic to adjust control parameters based on operating conditions.
A power supply circuit synchronizes output voltage slopes to prevent inrush currents during memory card insertion.
Parallel smaller capacitors reduce sub-threshold leakage in CMOS switches, extending hold time without increasing chip area.
A switching regulator uses phase feedback to stabilize operating frequency.
A power converter with a bypass mode enables efficient wireless energy transfer using n-type transistors.
Periodic charging of a small compensation capacitor maintains control accuracy while reducing silicon chip area and production costs.
Control circuitry adjusts switching frequency to schedule power transitions during noise-immune operational phases.
A digitally controlled switched mode power supply adjusts compensator parameters using time domain measurements to minimize overshoot and settling time.
A primary controller uses ripple cancellation and compensation circuits to generate gate signals that adjust power switch timing.
A control circuit detects switch node voltage change rates to generate opposing current pulses that eliminate output noise during high frequency switching.
A DC-DC converter uses a p-MOS switch as a reference for gate voltage supply to control parallel transistors.
A single-phase inverter topology uses a small film capacitor for power decoupling and voltage boosting.
A switching control circuit calculates a current control value to adjust dead times in a power supply.
Self-service reference voltage generation clamps transistor terminals, eliminating external power supplies while ensuring safe FinFET operation.
A main stage converter uses an integrated magnetic structure to combine transformer and choke windings on a single core.
Switching elements and coupling inductors enable dynamic linking of parallel DC links, preventing rectifier overload by limiting compensation currents.
A power supply system combines low-speed and high-speed outputs using a frequency blocking circuit to generate a stable voltage.
Dynamic threshold calculation resolves inconsistent protection across varying line input voltages while maintaining reliable maximum power delivery.
Dividing the input voltage range into sub-ranges via tap switching extends minimum duty cycle and reduces RMS current.
A DC-DC converter circuit uses a current limiter to constrain coil current independently of the switch duty cycle.
Segmented dual auxiliary power supply design eliminates mechanical switch delays while minimizing standby energy consumption through automated state switching.
Accuracy enhanced feedback network injects controlled ripple signals to stabilize regulated output voltage in buck switching regulators.
Primary-side drain voltage sampling calculates secondary output voltage without optocouplers, reducing feedback network complexity.
Segmented primary windings with intermediate taps enable bipolar operation that reduces ripple current and eliminates dead time.
A differential difference amplifier Type-III compensator reduces chip area by 60% in voltage-mode switching converters.