CMOS-Compatible Ternary Logic Element With Low-Power Switching
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Solution Overview
Problem
Existing ternary logic systems face challenges in compatibility with CMOS technology and high power consumption, making it difficult to develop efficient and integrated ternary logic elements.
Innovation Solution
A ternary logic element is designed comprising a transistor and a switching element, where the transistor includes a channel layer of silicon with specific doping configurations, and the switching element includes an emitter, base, and collector with silicon and dopant configurations that allow for low power consumption and compatibility with CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If carbon nanotube field effect transistors or graphene varistors are used to implement ternary logic, then three-state expression capability is achieved, but compatibility with CMOS technology is lost and power consumption increases
Solution Approach 1:
The patent introduces a floating gate as an intermediary element that enables ternary logic states (0, 1, 2) using standard CMOS transistors. The floating gate stores charge to represent different logic states, acting as a mediator between the binary transistor structure and ternary logic requirements, thus maintaining CMOS compatibility while achieving three-state expression.
Solution Approach 2:
The patent changes the electrical parameters of the transistor by introducing a floating gate that can hold different charge levels. This allows the transistor to exhibit three distinct conduction states (cut-off, linear, saturation) corresponding to ternary logic values, enabling ternary logic functionality without leaving the CMOS technology framework.
2Adaptability or versatility
If carbon nanotube field effect transistors or graphene varistors are used to implement ternary logic, then three-state expression capability is achieved, but power consumption increases
Solution Approach 1:
The floating gate serves as an energy-efficient intermediary that stores charge states representing ternary logic values. Unlike carbon nanotube or graphene devices that require continuous power to maintain states, the floating gate structure uses charge storage to maintain logic states without continuous power supply, significantly reducing power consumption while enabling ternary logic.
Solution Approach 2:
The floating gate structure enables the transistor to self-maintain its logic state through charge storage on the floating gate. Once a state is written, it is maintained without requiring continuous external energy input, making the system self-sufficient in maintaining its ternary logic states and reducing overall power consumption.
3Ease of manufacture
If conventional binary logic systems are used, then CMOS compatibility is maintained, but calculation efficiency is limited
Solution Approach 1:
The patent modifies the transistor's electrical characteristics by adding a floating gate that can store different amounts of charge. This creates three distinct conduction states (cut-off, linear, saturation) that correspond to ternary logic values 0, 1, and 2. By changing the parameter space from binary to ternary states, calculation efficiency is improved while maintaining CMOS compatibility.
Solution Approach 2:
The modified transistor structure serves multiple functions: it maintains compatibility with standard CMOS manufacturing processes while simultaneously providing ternary logic capability. The floating gate transistor can operate in different modes (cut-off, linear, saturation) to represent different logic states, making it a universal element that combines CMOS manufacturability with enhanced computational efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed ternary logic element achieves low power consumption and improved process efficiency, enabling high integration and compatibility with CMOS technology, thus overcoming the limitations of existing systems.
Implementation Method 1
The transistor may include a channel layer including silicon, an input electrode, an output electrode, and a control electrode. When a first control voltage is applied to the control electrode, a first voltage may be output, when a second control voltage different from the first control voltage is applied to the control electrode, a second voltage different from the first voltage may be output, and when a third control voltage different from the first control voltage and the second control voltage is applied to the control electrode, a third voltage different from the first voltage and the second voltage may be output.
Implementation Method 2
The switching element may include an emitter, a base extending from the emitter, and a collector extending from the base. The emitter, the base, and the collector may each include silicon, the emitter and the collector may each be doped with either an n-type dopant or a p-type dopant, and the base may be doped with the other type of dopant.
Data Source
AI summary
A ternary logic element including a transistor and a switching element. The transistor includes a channel layer including silicon, an input electrode, an output electrode, and a control electrode. The switching element includes an emitter, a base extending from the emitter, and a collector extending from the base. When a first control voltage is applied to the control electrode, the ternary logic element outputs a first voltage, and when a second control voltage different from the first control voltage is applied to the control electrode, the ternary logic element outputs a second voltage different from the first voltage, and when a third control voltage different from the first control voltage and the second control voltage is applied to the control electrode, the ternary logic element outputs a third voltage different from the first voltage and the second voltage.