Low-Voltage CMOS Tri-State Buffer With Fast Control Signal Discharge
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Solution Overview
Problem
Conventional low voltage CMOS process buffers are power-consumptive due to the lack of a high impedance state at the output terminal and suffer from long control signal falling times, leading to malfunctions.
Innovation Solution
A low voltage CMOS process tri-state buffer is designed with a logic device, a biasing device, and a switch device, which includes logic units for generating control signals to enable a high impedance state and a discharge device to manage the voltage falling time, allowing the output terminal to float when disabled, thus reducing power consumption and preventing malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the buffer uses a conventional two-state output design without high impedance state, then the buffer can continuously drive the output signal, but the buffer becomes more power-consumptive due to continuous DC current generation
Solution Approach 1:
The patent applies the dynamics principle by introducing a tri-state output design that allows the buffer to dynamically switch between three states: high voltage level, low voltage level, and high impedance state. The switch device (transistors T5 and T6) is controlled by control signals VG5 and VG6 to enable the output terminal to transition between these states based on the enable signal, thereby reducing power consumption during high impedance state while maintaining driving capability when needed.
2Device complexity
If the buffer uses a single discharge path for the control signal VG5, then the circuit structure is simple, but the discharge current is restricted and the voltage level falling time becomes longer causing malfunction
Solution Approach 1:
The patent applies the segmentation principle by dividing the discharge path into multiple parallel branches. Instead of a single discharge path, the control signal VG5 can be discharged through multiple transistors (T3 and T4) operating in parallel, which increases the total discharge current capability and reduces the voltage level falling time, thereby preventing malfunction while maintaining reasonable circuit complexity.
Data Source
AI summary
A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.