CMOS Ultra-Stressor Layer for Transistor Current Flow
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Solution Overview
Problem
In CMOS devices, the stress characteristics that enhance current flow for one type of transistor can degrade the performance of adjacent transistors, making it challenging to optimize current flow while minimizing adverse effects.
Innovation Solution
A semiconductor device with an ultra-stressor layer is fabricated by forming a tensile stress film over the source and drain areas of the NMOS portion and a compressive stress film over the PMOS portion, with a compressive stress etch stop layer and an inter-layer dielectric stressor layer to selectively impart stress, minimizing negative effects on adjacent devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform stress layer is applied over the entire CMOS device, then current flow is enhanced in one type of transistor, but performance of adjacent transistors is degraded
Solution Approach 1:
The patent applies different stress characteristics to different regions of the CMOS device. Specifically, a first stress characteristic is applied to the NMOS transistor region while a second, different stress characteristic is applied to the PMOS transistor region. This local differentiation allows each transistor type to receive optimized stress conditions without adversely affecting the other, resolving the contradiction between enhancing current flow in one transistor type and preventing performance degradation in adjacent transistors.
2Reliability
If stress engineering is applied to enhance current flow, then transistor performance is improved, but device complexity increases
Solution Approach 1:
The stress engineering structure is segmented into distinct regions corresponding to different transistor types. The patent divides the stress layer into a first stress layer for NMOS transistors and a second stress layer for PMOS transistors. This segmentation allows independent optimization of stress characteristics for each transistor type while maintaining a modular structure that manages device complexity through systematic regional differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances current flow in both p-channel and n-channel transistors, improving overall system performance and reliability by optimizing stress engineering in CMOS devices.
Implementation Method 1
A tensile stress film is formed over the source and drain areas of the NMOS portion and a compressive stress film is formed over the PMOS portion
Data Source
AI summary
A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS device, the ultra-stressor layer includes a compressive stress film over the source and drain regions and a tensile stress film over the poly region. In a preferred embodiment, the semiconductor device includes a PMOS transistor and an NMOS transistor forming a CMOS device and covered with an ultra stressor layer.