CMOS Varactor Segmentation for Increased Tuning Range
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Solution Overview
Problem
CMOS varactors face limitations in tuning range due to parasitic fringe capacitances, which increase with smaller channel lengths, restricting the Cmax/Cmin ratio and affecting performance in high-speed I/O systems and wireless communication.
Innovation Solution
Reducing fringe capacitance by modifying the source/drain structures, such as removing epitaxial layers and using even/odd mode excitation schemes, and configuring multiple gate varactors to minimize parasitic capacitance effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel length is reduced to enable further scaling, then device density and integration are improved, but parasitic fringe capacitance becomes larger relative to the main capacitance, decreasing the Cmax/Cmin ratio
Solution Approach 1:
The device is segmented into multiple gates (first gate and second gate) separated by a source/drain structure. This segmentation allows the total capacitance to be distributed across multiple capacitive elements, reducing the relative impact of parasitic fringe capacitance at each interface while maintaining the required total capacitance value.
Solution Approach 2:
A source/drain structure is introduced as an intermediary element between the first and second gates. This intermediary structure serves as a common terminal while electrically isolating the two gates, thereby reducing the parasitic fringe capacitance coupling between adjacent gates and improving the overall Cmax/Cmin ratio.
2Quantity of substance
If multiple gates are used to increase capacitance, then the Cmax value increases, but the parasitic fringe capacitance from source/drain structures also increases, limiting the tuning range
Solution Approach 1:
The varactor is divided into multiple independent gate sections (first gate and second gate) that can be independently controlled. Each gate forms its own capacitive element with the well, allowing the useful capacitance to scale with the number of gates while the parasitic fringe capacitance is distributed and reduced at each segmentation point.
Solution Approach 2:
The source/drain structure is extracted and positioned between the first and second gates to serve as a common terminal. This extraction separates the control functions of the two gates while minimizing the parasitic fringe capacitance between them, allowing each gate to contribute to the total capacitance without proportionally increasing parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the Cmax/Cmin ratio by up to 60% and widens the tuning range, improving frequency stability and supporting wider frequency applications, including high-speed I/O and wireless communication systems.
Implementation Method 1
Capacitors in general and varactors in particular operate on a principle of using two conductive plates or surfaces with an insulator in between. Varactors typically vary the electrical capacitance on one of the terminals (the signal terminal) in response to the voltage level on the other terminal (the control terminal).
Data Source
AI summary
A varactor is described that may be constructed in CMOS and has a high tuning range. In some embodiments, the varactor includes a well, a plurality of gates formed over the well and having a capacitive connection to the well, the gates comprising a first subset of the gates that are adjacent and consecutive and coupled to a positive pole of an excitation oscillation signal, and a second subset of the gates that are adjacent and consecutive and coupled to a negative pole of the excitation oscillation signal, and a plurality of source/drain terminals formed over the well and having an ohmic connection to the well, each coupled to a respective gate to receive a control voltage to control the capacitance of the varactor.