Single-Stage CMOS Voltage Quadrupler Circuit Design
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Solution Overview
Problem
Existing voltage quadrupler circuits occupy a large circuit area due to multiple stages and capacitors, leading to significant charge loss and inefficiency in voltage conversion, particularly when scaling up to quadruple the input voltage.
Innovation Solution
A single-stage voltage quadrupler circuit design utilizing a combination of n-channel and p-channel MOS transistors, level shifting circuits, and bootstrapped capacitors to achieve voltage quadrupling with reduced area requirements and minimized charge loss, operating with only two clock phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multi-stage cascaded voltage doubler circuits are used to achieve voltage quadrupling, then the desired output voltage (4*VIN) is obtained, but the circuit area occupied increases significantly due to multiple capacitors and stages
Solution Approach 1:
The patent combines multiple voltage doubling operations into a single integrated stage. The circuit uses four capacitors (C1-C4) and six transistors (M1-M6) working together in one stage to achieve voltage quadrupling, rather than using separate cascaded stages. This merging reduces the overall circuit area while maintaining the voltage quadrupling function.
Solution Approach 2:
The capacitors and transistors in the single-stage circuit perform multiple functions simultaneously. For example, capacitors C1 and C2 serve both as charge storage elements and as voltage boosting elements during different phases of the clock cycle. The transistors act as both switches and charge transfer elements, enabling the circuit to achieve voltage quadrupling with fewer components.
2Power
If multiple capacitors are used in cascaded stages for voltage quadrupling, then the voltage conversion is achieved, but charge loss increases due to threshold voltage drops across transistor switches
Solution Approach 1:
The patent introduces bootstrapped capacitors (Cbs1, Cbs2) as intermediary elements to transfer charge between the main capacitors and the output. These bootstrapped capacitors are charged to higher voltages during specific clock phases and then used to boost the output voltage, reducing the threshold voltage drops that would otherwise occur across the transistor switches. This intermediary mechanism minimizes charge loss and improves conversion efficiency.
3Power
If the number of stages is increased for voltage quadrupling, then the output voltage magnitude increases, but the complexity of the circuit increases
Solution Approach 1:
The patent employs dynamic control of the transistors using two-phase clock signals (CK and CKN). The transistors are switched on and off in specific sequences during each clock cycle to achieve voltage quadrupling. This dynamic operation allows the circuit to perform multiple voltage boosting operations within a single stage, reducing the need for additional static circuit stages and simplifying the overall circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The single-stage circuit effectively quadruples the input voltage while reducing the overall circuit area and charge loss, achieving a more efficient voltage conversion compared to multi-stage cascaded designs.
Implementation Method 1
a first bootstrapping capacitor having a first plate coupled to the second node and a second plate coupled to receive the level shifted first clock signal
Implementation Method 2
a first boost capacitor having a first plate coupled to the first node and a second plate coupled to receive a first clock signal
Data Source
AI summary
A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.