CMP Planarization for Semiconductor Substrate Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for manufacturing semiconductor devices with stacked structures face challenges in achieving high electrical reliability due to inadequate bonding of conductive patterns and insulating interlayers, leading to defects and uneven interfaces.
Innovation Solution
The method involves forming conductive and barrier layers on substrates, followed by chemical mechanical polishing to create specific patterns, and then bonding these substrates with plasma treatment, ensuring that conductive patterns are in contact while barrier layers are not, thus enhancing the interface smoothness and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding methods are used to bond substrates with insulating interlayers containing conductive patterns, then the bonding process is simple, but the electrical reliability is poor due to inadequate bonding and uneven interfaces
Solution Approach 1:
The patent applies preliminary action by performing chemical mechanical polishing (CMP) on the conductive patterns and insulating interlayers before bonding. This pre-treatment creates uniformly flattened surfaces with controlled height differences, ensuring optimal bonding conditions are established in advance. The CMP process removes surface irregularities and prepares the interfaces for high-quality bonding, thereby improving electrical reliability without requiring complex bonding procedures.
Solution Approach 2:
The patent employs parameter changes by precisely controlling the height difference between conductive patterns and insulating interlayers through CMP processing. By adjusting polishing parameters and layer thicknesses, the invention creates specific height relationships (e.g., 0-5 μm, 5-10 μm ranges) that optimize both bonding quality and electrical performance. This controlled parameter adjustment resolves the contradiction by enabling reliable bonding through quantitative surface characterization rather than qualitative visual inspection.
2Manufacturing precision
If chemical mechanical polishing is performed to create specific patterns with controlled height differences, then the interface smoothness and bonding quality improve, but the manufacturing process becomes more complex
Solution Approach 1:
The CMP process is performed as a preliminary action before bonding to create uniformly flattened surfaces. By conducting the polishing operation in advance, the patent ensures that surface irregularities are eliminated before the bonding step, achieving high interface smoothness without adding complexity to the bonding process itself. The preliminary CMP creates optimal bonding surfaces that simplify subsequent assembly operations.
Solution Approach 2:
The chemical mechanical polishing process is self-regulating through the interaction between abrasive particles, chemical slurry, and the surfaces being polished. The CMP process automatically adjusts to surface conditions, maintaining consistent material removal rates and achieving uniform flatness across large areas. This self-service characteristic reduces the need for complex process control systems while maintaining high manufacturing precision.
3Reliability
If the top surface of the conductive pattern is made higher than the insulating interlayer, then the bonding contact area increases and electrical reliability improves, but the risk of galvanic corrosion increases
Solution Approach 1:
The patent applies parameter changes by precisely controlling the height difference between conductive patterns and insulating interlayers within specific ranges (e.g., 0-5 μm, 5-10 μm). This quantitative control optimizes the bonding contact area to improve electrical reliability while simultaneously limiting the exposure of conductive materials to environments that could cause galvanic corrosion. The controlled height parameter balances both benefits and risks.
Solution Approach 2:
The invention applies local quality by creating different surface heights at different locations: the conductive pattern top surface is elevated relative to the insulating interlayer to maximize bonding contact area, while the sidewalls and other regions maintain appropriate height relationships to prevent corrosion. This localized height differentiation optimizes bonding performance in contact regions while minimizing corrosion risk in exposed regions.
4Strength
If multiple layers including barrier layers and conductive layers are formed and polished, then the bonding strength and interface quality improve, but the manufacturing time and cost increase
Solution Approach 1:
The patent merges multiple functions into a single CMP process step that simultaneously polishes the conductive layer, barrier layer, and insulating interlayer to create a uniformly flattened surface. By combining these polishing operations into one integrated process, the invention achieves high interface quality and bonding strength without proportionally increasing manufacturing time. The merged CMP process eliminates the need for separate polishing steps for each layer.
Solution Approach 2:
The CMP process operates continuously to remove material from multiple layers simultaneously, maintaining a constant polishing action across the entire surface assembly. This continuous useful action ensures that all layers are polished to the required precision in a single uninterrupted operation, maximizing efficiency and reducing total manufacturing time compared to sequential polishing of individual layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with improved electrical reliability by ensuring even interfaces and strong bonding forces, reducing defects and galvanic corrosion, and maintaining the integrity of the conductive patterns and insulating layers.
Implementation Method 1
the first conductive layer and the first barrier layer are chemical mechanical polished to expose a top surface of the first insulating interlayer
Implementation Method 2
A plasma treatment is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively
Data Source
AI summary
A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.