CMP Polishing Pad Laminate Structure for Wafer Uniformity
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Solution Overview
Problem
Current chemical mechanical polishing pads for semiconductor devices face challenges in achieving optimal polishing rates and within-wafer non-uniformity, particularly for silicon oxide and tungsten, due to inadequate control over compression and wetting characteristics.
Innovation Solution
A polishing pad comprising a laminate structure with a polishing layer, an adhesive layer, and a cushion layer, where the initial load resistivity and compressive elasticity are optimized to ensure excellent polishing performance by maintaining a specific thickness ratio under varying stress loads, thereby minimizing scratches and ensuring consistent polishing precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the polishing pad uses conventional compression characteristics, then the structure is simple, but the polishing rate and within-wafer non-uniformity are insufficient
Solution Approach 1:
The polishing pad is divided into multiple functional layers including a polishing layer, adhesive layer, and cushion layer, each with specific thickness ratios (polishing layer 30-70 μm, adhesive layer 5-20 μm, cushion layer 20-50 μm). This segmentation allows each layer to perform its specific function optimally, resulting in improved polishing rate and within-wafer non-uniformity while maintaining manageable structural complexity through standardized layer configurations.
2Productivity
If the polishing pad optimizes compression characteristics for high polishing rate, then productivity improves, but manufacturing precision control becomes more difficult
Solution Approach 1:
The patent specifies precise parameter ranges for the laminate structure: initial load resistivity (LRL) of 85-95%, compressive elasticity (CEL) of 5-15%, and specific thickness ratios between layers. By controlling these parameters within defined ranges rather than exact values, the invention achieves high polishing rates while maintaining manufacturability and thickness control precision.
3Manufacturing precision
If the polishing pad increases compression resistance, then within-wafer non-uniformity decreases, but polishing rate may be reduced
Solution Approach 1:
The polishing pad uses a composite laminate structure combining materials with different properties: a polishing layer for material removal, an adhesive layer for bonding, and a cushion layer for compression resistance. This composite structure achieves both high polishing rate and low within-wafer non-uniformity (≤5 μm) by synergistically combining the functions of different materials in specific thickness ratios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized polishing pad achieves enhanced polishing rates and reduced within-wafer non-uniformity, leading to higher quality semiconductor devices by maintaining consistent performance and minimizing defects such as scratches.
Implementation Method 1
the compression characteristics and wetting characteristics of the polishing pad are one of the very important factors among the various factors that determine the surface characteristics of a semiconductor substrate
Implementation Method 2
the compression characteristics and wetting characteristics of the polishing pad are one of the very important factors among the various factors that determine the surface characteristics of a semiconductor substrate
Implementation Method 3
a chemical mechanical polishing pad is a polishing pad for use in a chemical mechanical planarization (CMP) process that chemically and mechanically polishes the surface of a semiconductor substrate
Data Source
AI summary
Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductor devices. The polishing pad may secure excellent polishing rate and within-wafer non-uniformity by controlling the physical properties such as initial load resistivity and compressive elasticity of the cushion layer and/or the laminate as defined by Equations 1 and 2:LRL(%)=T1L-T2LT1L-T3L×100[Equation1]CEL(%)=T4L-T3LT2L-T3L×100.[Equation2]
