CMUT-CMOS Wafer Bonding Without TSVs or Thermal IC Damage
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Solution Overview
Problem
Current methods for integrating Capacitive Micromachined Ultrasonic Transducers (CMUTs) with CMOS wafers face challenges in achieving strong bonds without damaging the integrated circuits, and often require complex and costly processes like through-silicon vias (TSVs).
Innovation Solution
A wafer-level process involving two bonding steps is used, where high-temperature bonding forms sealed cavities between silicon-on-insulator (SOI) wafers, and subsequent low-temperature bonding integrates these with a CMOS wafer, avoiding the need for TSVs by using alternative structures for electrical connections and thinning techniques to achieve a compact, ultrasonic transducer device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high-temperature bonding is used to form sealed cavities, then bond strength is improved, but CMOS ICs may be damaged
Solution Approach 1:
The bonding process is divided into two separate stages: first, high-temperature bonding is used to form sealed cavities between SOI wafers; second, low-temperature bonding is used to integrate the engineered substrate with the CMOS wafer. This segmentation allows each bonding step to use optimal temperature conditions without compromising the other component.
Solution Approach 2:
The sealed cavities are formed in advance between SOI wafers using high-temperature bonding before the CMOS wafer is introduced. This preliminary action completes the high-temperature bonding step before the CMOS ICs are exposed to thermal processes, preventing damage to the integrated circuits.
2Reliability
If through-silicon vias (TSVs) are used for electrical connections, then electrical connectivity is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The complex TSV structure is removed and replaced with simpler alternative connection methods. The patent uses bonded wafer structures and metal layers that can provide electrical connectivity without requiring through-silicon via formation, thereby reducing manufacturing steps and device complexity.
Solution Approach 2:
The patent employs standard CMOS-compatible metal layers and bonding structures that are simpler and more cost-effective than TSVs. These alternative connection structures achieve the necessary electrical connectivity without the high complexity and cost associated with through-silicon via fabrication.
3Adaptability or versatility
If wafer bonding is used to integrate CMUTs with CMOS wafers, then integration is improved, but thermal damage to CMOS ICs occurs
Solution Approach 1:
The integration process is segmented into two distinct bonding operations: first bonding SOI wafers together at high temperature to create engineered substrates with sealed cavities, then bonding these engineered substrates to CMOS wafers at low temperature. This segmentation enables integration while protecting CMOS ICs from thermal damage.
Solution Approach 2:
The bonding temperature parameter is changed between the two bonding steps. The first bonding step uses high temperature (suitable for SOI wafer bonding), while the second bonding step uses low temperature (suitable for protecting CMOS ICs). This parameter change allows both integration and IC protection to be achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of thin, compact CMOS ultrasonic transducers with integrated CMUTs, reducing manufacturing costs and complexity while maintaining structural integrity and avoiding damage to CMOS ICs, allowing for scalable and high-yield production.
Implementation Method 1
bonding a first SOI wafer with a second SOI wafer... bonding the engineered substrate with a CMOS wafer
Implementation Method 2
Relatively high temperatures may be used, for example during an anneal, to facilitate achieving a strong bond
Implementation Method 3
A handle layer of one of the two SOI wafers of the engineered substrate may then be removed
Data Source
AI summary
Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.