COA Substrate Manufacturing Method Reducing Capacitive Coupling
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Solution Overview
Problem
The manufacturing process of COA substrates is complicated and costly due to the need for multiple passivation layers and capacitive coupling effects between scan and data lines, which increases production expenses and complexity.
Innovation Solution
A COA substrate manufacturing method that forms a color resist layer before the second metal layer, eliminating the need for an additional passivation layer and reducing capacitive coupling by modifying the layout of electrodes and transparent conductive layers, thereby simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a passivation layer is disposed between drain electrodes and color resist layer in conventional COA substrate, then electrical insulation is improved, but manufacturing process complexity and cost increase
Solution Approach 1:
The gate insulation layer is designed to serve dual functions: as the gate dielectric for the TFT and as the passivation layer insulating the color resist layer from the drain electrode. This merging of functions eliminates the need for a separate passivation layer, reducing manufacturing process complexity while maintaining electrical insulation requirements.
Solution Approach 2:
The gate insulation layer performs multiple roles simultaneously: (1) as the gate dielectric between gate electrode and active layer, (2) as the passivation layer providing electrical insulation between the color resist layer and drain electrode, and (3) as a structural layer supporting the color resist pattern formation. This multi-functionality reduces the total number of layers and manufacturing steps.
2Area of stationary object
If scan lines and data lines are placed close together in conventional COA substrate, then aperture ratio is improved, but capacitive coupling effects occur at intersection areas
Solution Approach 1:
The gate insulation layer acts as an intermediary dielectric layer between the scan lines and data lines at their intersection areas. By ensuring proper thickness and dielectric properties of this layer, capacitive coupling between the closely-spaced lines is reduced while allowing the lines to maintain small intervals for high aperture ratio.
Solution Approach 2:
The invention optimizes the thickness and dielectric constant parameters of the gate insulation layer to balance two competing requirements: sufficient thickness to reduce capacitive coupling between closely-spaced scan and data lines, while maintaining thin enough profile to allow small line intervals for high aperture ratio. The color resist layer pattern formation parameters are also adjusted accordingly.
Data Source
AI summary
A COA (Color filter On Array) substrate and a manufacturing method using the same are disclosed. The method includes: forming a first metal layer, a gate insulation layer, a color resist layer, an active layer, a second metal layer, a passivation layer, a via hole, and a transparent conductive layer in order. The via hole is used for connecting to the transparent conductive layer with the second metal layer. The transparent conductive layer is formed on the passivation layer. A gate electrode is formed by pattering the first metal layer. A drain electrode and a source electrode are formed by pattering the second metal layer. In the present invention, the color resist layer is made before the second metal layer.