Die-bonding Substrate for High-Density COB White Light Source
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current white-light LED sources face issues with thermal aging due to poor thermal conductivity, leading to reduced light quality and stability, and they struggle to achieve high luminous flux and power efficiency.
Innovation Solution
A die-bonding substrate with an optimized configuration of array chips and conductive lines, combined with a reflective dam body and solid-state phosphor, enhances heat drainage and light uniformity, enabling high-density and high-power integration of the light source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fluorescent powder gel is used to coat excitation chips, then the white light source can be easily manufactured, but the poor thermal conducting performance leads to thermal aging and reduced light quality
Solution Approach 1:
The patent removes the fluorescent powder gel layer from the structure, replacing it with a reflective dam body and solid-state phosphor arrangement. This extraction eliminates the thermal conductivity problem while maintaining the white light generation function through alternative means (direct phosphor excitation without gel medium).
Solution Approach 2:
The patent introduces a reflective dam body as an intermediary structure between the excitation chips and the environment. This reflective structure serves as a mediator that redirects light and heat away from the chip array, improving thermal management and light extraction efficiency without requiring thermal-conductive gel.
2Device complexity
If a single chip is used, then the structure is simple, but the luminous flux is insufficient for illumination applications
Solution Approach 1:
The patent divides the light source into multiple discrete excitation chips arranged in an array configuration. Each chip operates independently but contributes to the total luminous flux. This segmentation allows the system to achieve high brightness levels required for illumination while maintaining manageable structural complexity through standardized chip designs and systematic arrangement.
Solution Approach 2:
The patent combines multiple excitation chips into a single integrated array structure mounted on a common substrate with shared reflective and phosphor elements. This merging approach consolidates the functional output of individual chips to achieve the required luminous flux for illumination applications while sharing common support infrastructure.
3Productivity
If large-power LED modules are developed with high integration, then the luminous flux increases, but the heat drainage becomes more challenging
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat management by positioning the chip array in a spatial configuration that utilizes vertical and lateral dimensions. The reflective dam body and phosphor distribution create multiple light extraction paths and heat dissipation routes in different dimensions, effectively managing thermal load in high-power integrated modules.
Solution Approach 2:
The patent converts the harmful heat and light radiation from the chip array into beneficial effects by using the reflective dam body to redirect both. The same structure that manages light extraction also facilitates heat dissipation by directing thermal energy away from the chip junctions, turning potential thermal problems into active heat management features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures effective light output with increased luminous flux and efficiency, reducing manufacturing costs and improving the reliability of the light source by optimizing heat dissipation and chip arrangement.
Implementation Method 1
the conductive line layer includes a chip welding wire region and an external electrode region, which are electrically connected to each other; the chip welding wire region is composed of multiple conductive lines
Implementation Method 2
a solid-state phosphor located in the light exit direction of the die-bonding substrate
Data Source
AI summary
A die-bonding substrate has a substrate, and a conductive line layer and a chip array provided on the substrate. The conductive line layer includes a chip welding wire region and an external electrode region connected with each other. The chip welding wire region is composed of multiple conductive lines, wherein the central conductive line located in the central position of the chip welding wire region is a straight line section. The conductive lines arranged at both sides of the central conductive line are straight line sections at both ends, and arc sections curved outwards in the middle, so that the entire chip welding wire region forms a circular area. The array chips are arranged inside the circular area, and are electrically connected with the conductive lines arranged at both sides. The entire chip welding wire region can also form a rectangular area.