Code Portion Profiling for Dynamic Instruction Translation
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Solution Overview
Problem
Existing micro-processing systems face inefficiencies in translating non-native ISA instructions due to performance overhead, necessitating targeted optimization of frequently executed code to amortize this overhead.
Innovation Solution
The system employs code portion profiling to dynamically form native translations by using an on-core hardware decoder and branch history tables, identifying and prioritizing code portions for translation based on execution frequency and control flow analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If native translations are created for non-native ISA instructions, then execution performance is improved, but translation overhead increases
Solution Approach 1:
The system performs preliminary code portion profiling to identify frequently executed non-native ISA instructions before creating native translations. By analyzing execution frequency and control flow patterns in advance, the system prioritizes translation creation for the most impactful code portions, ensuring that translation overhead is amortized over the highest value code sections.
Solution Approach 2:
Instead of translating all non-native instructions uniformly, the system applies selective translation to specific code portions identified through profiling. Each code portion is evaluated individually based on its execution frequency and control flow characteristics, creating native translations only for those sections that provide the greatest performance benefit.
2Productivity
If code portion profiling is performed to identify frequently executed code, then translation efficiency is improved, but profiling complexity increases
Solution Approach 1:
The profiling mechanism leverages existing hardware decoder execution traces and control flow information that are already being collected during normal processor operation. By using the hardware decoder's own execution data and integrating profiling with the existing translation formation process, the system avoids adding separate complex profiling infrastructure.
Solution Approach 2:
The system merges the code portion profiling function with the existing hardware decoder and translation formation processes. The profiling data structure is integrated into the hardware decoder's operation, and the control flow analysis is combined with the translation creation algorithm, eliminating the need for separate profiling systems.
3Adaptability or versatility
If all non-native ISA instructions are translated, then coverage is maximized, but performance overhead increases
Solution Approach 1:
The system applies partial translation rather than complete translation of all non-native ISA instructions. By using code portion profiling to identify only the frequently executed and high-value code sections, the system creates native translations for a subset of instructions that provide the greatest performance improvement, leaving less frequently executed instructions to be handled by the hardware decoder.
Data Source
AI summary
The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.