Co-doped Semiconductor Devices for Charge Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor power devices with charge compensation structures face challenges in achieving low on-state resistance and high breakdown voltages while minimizing chip area and manufacturing complexity, particularly in tuning the doping concentration of n-type JTE regions for edge-termination structures.
Innovation Solution
The semiconductor device incorporates a co-doped semiconductor layer with alternating n-type and p-type dopants, forming drift portions and compensation regions, and an edge termination region with a dielectric layer, where more p-type dopants are diffused into the intrinsic semiconductor material in trenches, creating a wider horizontal extension in the peripheral area to enhance reverse blocking capability and stabilize charge compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the doping concentration of the n-type JTE region is adjusted to achieve high breakdown voltages, then the reverse blocking capability is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent adjusts the doping concentration parameter of the n-type JTE region to achieve high breakdown voltages and improved reverse blocking capability. By optimizing this parameter, the device achieves better reliability without requiring complex manufacturing processes
Solution Approach 2:
The patent applies different doping concentrations in different regions: the n-type JTE region has a specific doping concentration optimized for breakdown voltage, while other regions have different doping levels suited to their functions. This local optimization allows high reliability in the peripheral area without complicating the overall manufacturing process
2Reliability
If the peripheral area is enlarged to improve reverse blocking capability, then the breakdown voltage increases, but the chip area increases and costs increase
Solution Approach 1:
The patent enhances the reverse blocking capability specifically in the peripheral area through optimized doping structures (n-type and p-type JTE regions with specific doping concentrations), rather than enlarging the entire chip. This allows improved reliability without proportionally increasing the chip area
Solution Approach 2:
By changing the doping concentration parameters in the peripheral region, the patent achieves high breakdown voltages and reverse blocking capability in a compact peripheral area, avoiding the need to significantly enlarge the chip area
3Reliability
If the doping concentration of the n-type JTE region is increased to improve breakdown behavior, then the reverse blocking capability is enhanced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the doping concentration parameter of the n-type JTE region to achieve good breakdown behavior while maintaining reasonable manufacturing precision requirements. The selected doping concentration balances performance with manufacturability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces on-state resistance, increases breakdown voltage, and simplifies manufacturing by stabilizing the breakdown behavior and compensating for doping imbalances, ensuring efficient and reliable operation of the semiconductor device.
Implementation Method 1
more p-type dopants are diffused into the intrinsic semiconductor material in trenches
Implementation Method 2
The compensation principle is based on a mutual compensation of charges in n- and p-doped regions
Implementation Method 3
a dielectric layer arranged at the first side and forming a first interface with the edge termination region and a second interface with the first semiconductor region
Implementation Method 4
The drift portions are in Ohmic connection with the drain metallization. The compensation regions are in Ohmic connection with the source metallization
Implementation Method 5
an edge termination region of the second conductivity type arranged at the first side... having, in a horizontal direction parallel to the first side, a horizontal extension which is larger than an extension of the compensation regions
Data Source
AI summary
A method for forming a field-effect semiconductor device includes providing a wafer having a substantially compensated semiconductor layer extending to an upper side and including a semiconductor material which is co-doped with n-type dopants and p-type dopants. A peripheral area laterally surrounding an active area are defined in the wafer. Trenches in the active area are filled with a substantially intrinsic semiconductor material. More p-type dopants than n-type dopants are diffused from the compensated semiconductor layer into the intrinsic semiconductor material to form a plurality of p-type compensation regions in the trenches which are separated from each other by respective n-type drift portions. P-type dopants are introduced at least into a semiconductor zone of the peripheral area, so that the semiconductor zone and a dielectric layer on the upper side form an interface. A horizontal extension of the interface is larger than a vertical extension of the trenches.