Chip-on-Film Driving Chip Layout for Tight Display Bonding Space
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Solution Overview
Problem
Current display technologies face insufficient bonding spaces for chip on film (COF) assemblies due to increased data signal requirements with higher resolution displays, particularly in 8K products, which necessitate more COFs in a limited panel size.
Innovation Solution
The proposed solution involves a chip on film assembly with a substrate having input and output terminals, where multiple driving chips are integrated and arranged in a staggered or layered configuration to optimize pin layout, allowing for efficient bonding of COFs to the display panel, thereby improving space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the display panel is improved, then the display quality is enhanced, but the number of COFs required increases, leading to insufficient bonding spaces
Solution Approach 1:
Multiple driving chips are integrated onto a single COF substrate, combining multiple independent driving functions into one unified assembly. This merging approach reduces the total number of separate COF assemblies needed, thereby freeing up bonding spaces on the display panel while maintaining the required driving capabilities for high-resolution displays.
Solution Approach 2:
The patent utilizes multi-layer substrate structures and three-dimensional arrangements of driving chips and pins. By stacking components across multiple layers and utilizing vertical space, the design accommodates more pins and driving chips within the same planar bonding area, effectively increasing bonding capacity without expanding the panel footprint.
2Quantity of substance
If more output pins are arranged on the COF to support higher resolution, then the data signal capacity is improved, but the pin arrangement space becomes more constrained
Solution Approach 1:
The patent employs multi-layer substrate structures where pins are arranged across multiple vertical layers. This three-dimensional pin arrangement allows significantly more pins to be packed into the same planar bonding area by utilizing the vertical dimension, thereby supporting high-resolution displays without constraining the pin arrangement space.
Solution Approach 2:
Multiple rows of pins are nested in a staggered configuration where pins in adjacent rows are offset from each other. This nesting pattern maximizes pin density by efficiently utilizing available space, allowing more pins to be arranged within the same COF width while maintaining proper electrical connections.
Data Source
AI summary
A chip on film assembly, a display panel, and a display module are disclosed. The chip on film assembly includes a substrate, an input terminal disposed on a first end of the substrate, a plurality of output terminals disposed on a second end of the substrate, wherein the second end is opposite to the first end, and a plurality of driving chips disposed on a surface of the substrate. The driving chips are electrically connected to the input terminal and are electrically connected to the output terminals by one to one, so space utilization of chip on films (COFs) can be improved, and a problem of insufficient COF bonding spaces for high-resolution products can be solved.