COF Package Tape Substrate Vertical Stacking
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Solution Overview
Problem
Existing semiconductor chip packaging technologies face challenges in reducing chip size while ensuring high reliability, particularly with increasing output terminals and wiring complexity, leading to inefficient use of space and potential reliability issues.
Innovation Solution
A COF package with a tape substrate design that includes external and internal input/output terminals, wirings, and dummy wiring to minimize chip area and enhance reliability by optimizing electrode placement and wiring patterns, reducing internal wiring impedance and area, and reinforcing connections through dummy electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of output terminals per driver is increased to meet display demands, then the driver functionality is improved, but the area of the semiconductor element increases significantly
Solution Approach 1:
The patent transitions from planar chip mounting to three-dimensional vertical stacking by introducing multiple layers of tape substrates (first and second tape substrates) with intermediate substrates between them. This allows the semiconductor element to be mounted on one substrate while other substrates are stacked above, effectively utilizing the vertical dimension to accommodate increased terminal count without expanding the horizontal chip area.
Solution Approach 2:
The patent divides the tape substrate into multiple segments or layers (first tape substrate, second tape substrate, intermediate substrate) that can be stacked vertically. This segmentation allows the wiring areas and terminals to be distributed across multiple layers, reducing the wiring density and area required on any single layer while maintaining the total number of output terminals.
2Area of stationary object
If the chip area is reduced to minimize packaging size, then the packaging compactness is improved, but the interval between adjacent electrodes becomes very narrow
Solution Approach 1:
By stacking tape substrates vertically with intermediate substrates, the patent creates additional vertical space that allows for larger electrode intervals on each individual layer. The vertical separation between layers compensates for the reduced horizontal chip area, maintaining adequate electrode spacing while minimizing the overall packaging footprint.
Solution Approach 2:
The patent introduces dummy electrodes and dummy wirings in advance during the design stage. These dummy structures are strategically placed to maintain proper spacing and intervals between functional electrodes, ensuring that even with reduced chip area, the actual signal-carrying electrodes maintain adequate intervals for reliable operation.
3Reliability
If dummy wiring and dummy electrode are added to reduce internal wiring impedance, then the wiring reliability is improved, but the chip area increases
Solution Approach 1:
The patent places dummy wiring and dummy electrodes on vertically stacked tape substrates rather than consuming additional horizontal chip area. The intermediate substrates provide vertical separation that allows dummy structures to be positioned in three-dimensional space, reducing their impact on the planar chip area while still achieving the goal of lowering internal wiring impedance through extended wiring paths.
Data Source
AI summary
A COF package having a tape substrate including external input terminals and external output terminals provided in a chip non-mounting area, input wirings connected to the external input terminals respectively, output wirings connected to the external output terminals respectively, internal input wirings which are provided from the chip non-mounting area to a chip mounting area and provided between the input wirings and which are connected to the external input terminals, respectively, and a dummy wiring provided from the chip non-mounting area to the chip mounting area and provided between the internal input wirings; and a semiconductor chip including input electrodes connected to the input wirings respectively, output electrodes connected to the output wirings respectively, internal input electrodes connected to the internal input wirings respectively, and a dummy electrode provided spaced from each input electrode along one side of the chip surface, and connected to the dummy wiring.