Collapsed Multi-Integration Package for High Density IC Assembly
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving smaller footprints, higher integration density, reduced production time, and cost-effectiveness while addressing issues like EMI radiation, thermal loads, and second-level assembly reliability stresses in portable electronics.
Innovation Solution
The method involves a base substrate with a central integrated circuit and side packages mounted peripherally, both encapsulated to form a planar surface, allowing for increased I/O count and design flexibility through co-planar surfaces and vertical connectors, which also reduces parasitic inductance and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple components are integrated into a single package to increase functionality and integration density, then the integration density and functionality are improved, but the manufacturing complexity and error risk increase
Solution Approach 1:
The package is divided into a base package and multiple side packages that can be manufactured and tested independently, then assembled together. This segmentation allows each component to be optimized separately while achieving high integration density in the final assembly.
Solution Approach 2:
Side packages are mounted on peripheral regions of the base substrate, effectively nesting multiple functional units within a single package footprint. This nesting approach increases integration density without proportionally increasing the overall package area.
2Reliability
If side packages are mounted on peripheral regions with coplanar surfaces to increase I/O count and reduce parasitic inductance, then the electrical performance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The coplanar surface requirement is applied locally only to the regions where side packages interface with the base substrate, rather than requiring the entire package to be perfectly flat. This localized approach maintains electrical performance while reducing overall manufacturing complexity.
Solution Approach 2:
By ensuring coplanar surfaces at the interface regions, the patent creates equipotential contact areas that minimize parasitic inductance and improve signal integrity, while allowing other regions of the package to have varying heights for functional components.
3Ease of manufacture
If a planar surface is formed over all components to simplify assembly, then the ease of manufacture is improved, but the design flexibility and I/O count are limited
Solution Approach 1:
The patent transitions from a traditional two-dimensional planar arrangement to a three-dimensional configuration where side packages are vertically positioned on peripheral regions. This dimensional change allows multiple components to coexist in the same footprint while maintaining a planar top surface for simplified assembly.
Solution Approach 2:
The package structure allows for dynamic configuration where side packages can be selectively positioned on different peripheral regions depending on the specific application requirements, providing design flexibility while maintaining the overall planar assembly interface.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a central integrated circuit over the base substrate; mounting a side package having a side package substrate along a peripheral region of the base substrate and laterally peripheral to the central integrated circuit with the side package substrate coplanar with the central integrated circuit; and encapsulating the central integrated circuit and the side package above the base substrate with a base encapsulation to form a planar surface over the central integrated circuit and the side package facing away from the base substrate.