Column-Parallel A/D Counting for In-Sensor Multiply-Accumulate
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Solution Overview
Problem
The existing AD conversion systems, particularly those using the reference signal comparison type combined with column parallel output, face challenges in managing counter area size due to the need for count mode switching and inefficient multiply-accumulate processing, which hinders high-quality image creation and increases circuit complexity.
Innovation Solution
A mechanism that performs multiply-accumulate processing, including difference and addition/subtraction processing, simultaneously with AD conversion using a reference-signal generating unit, a comparing unit, and a count unit, where count processing is done in parallel with comparison processing, and the count mode is applied uniformly for both subtraction and addition elements, allowing for efficient digital data acquisition without increasing counter area size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If count mode switching mechanism is adopted for difference processing during AD conversion, then difference processing function is achieved, but counter area size increases
Solution Approach 1:
The counter unit is designed to perform both AD conversion counting and difference processing counting using the same counting mechanism. By making the counter unit universal and capable of handling multiple functions without requiring separate count mode switching mechanisms, the patent avoids increasing counter area size while still achieving difference processing capability.
Solution Approach 2:
The patent combines the AD conversion function and difference processing function into a single integrated counter unit. By merging these functions and sharing the same counting resources, the design eliminates the need for separate count mode switching mechanisms that would increase area, while maintaining both processing capabilities.
2Adaptability or versatility
If separate count mode mechanisms are provided for all counter units, then difference processing is enabled, but device complexity increases
Solution Approach 1:
The counter unit is designed as a universal module that can handle both AD conversion and difference processing without requiring separate count mode switching mechanisms. This universality reduces device complexity by eliminating redundant circuitry while maintaining full processing capability.
3Measurement precision
If AD conversion and multiply-accumulate processing are performed separately, then processing accuracy is maintained, but processing speed decreases
Solution Approach 1:
The patent enables continuous processing by performing AD conversion and multiply-accumulate operations simultaneously in parallel. The counter unit continuously counts during the entire process without interruption, maintaining both accuracy through proper counting methodology and speed through concurrent execution of operations.
Solution Approach 2:
The counter unit is prepared and configured in advance to handle both AD conversion and difference processing functions. By having the counter unit ready and capable of handling multiple functions simultaneously, the system can proceed with processing without waiting for sequential completion of individual steps, thereby improving processing speed while maintaining accuracy.
Data Source
AI summary
A data processing device includes a comparing unit that compares a reference signal and respective processing object signals, a count-period control unit that determines a count period to perform count processing, a count unit that performs the count processing in the count period designated by the count-period control unit, stores a count value, applies the count processing to both a subtraction element and an addition element in an identical mode of any one of an up-count mode and a down-count mode, and starts the count processing for a following processing object signal using a count value for a preceding processing object signal as an initial value, and a correcting unit that corrects digital data of a multiply-accumulate result of the plural processing object signals to digital data in which a count value is corrected.