Combiner Latch Circuit for Stable Signal Swing at High Speed
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Solution Overview
Problem
High speed latches in wireless transceivers face challenges with operational functionality dependency on output signal swing and load variations, leading to reduced performance at higher frequencies.
Innovation Solution
A combiner latch circuit and latching system that minimizes functional dependency on output signal swing and load variations by selecting states based on input and clock signals, using a regenerative device and differential clock signals to achieve a divide-by-two function with reduced component count and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the output load is reduced at higher frequencies, then the signal swing is maintained, but the circuit operation functionality becomes more complex
Solution Approach 1:
The patent implements dynamic load adjustment through a variable resistance element controlled by a multi-bit digital controller. The load resistance is dynamically adjusted based on operating frequency to maintain signal swing, with the controller setting appropriate resistance values automatically as frequency changes. This dynamic adaptation resolves the contradiction by making the load variable rather than fixed.
Solution Approach 2:
The patent changes the resistance parameter of the load element to maintain circuit functionality across different operating conditions. By varying the resistance value through digital control, the circuit adapts to different frequencies while maintaining proper signal swing and operation, thus resolving the contradiction between maintaining signal integrity and keeping circuit operation simple.
2Use of energy by moving object
If the number of components is reduced, then power consumption decreases, but the ability to maintain signal swing at high frequencies is compromised
Solution Approach 1:
The patent employs a multi-bit digital controller that serves multiple functions: it controls the variable resistance element for load adjustment, manages frequency-dependent operations, and maintains signal swing across different operating conditions. This multi-functional component reduces the need for separate dedicated circuits, thereby reducing overall component count and power consumption while maintaining signal integrity.
Solution Approach 2:
The variable resistance element dynamically adjusts its resistance based on frequency and operational requirements, allowing the circuit to maintain signal swing without requiring additional static components. This dynamic behavior enables the circuit to adapt efficiently, reducing power consumption while preserving signal quality across frequency ranges.
3Illumination intensity
If variable resistance element is used for load adjustment, then signal swing is maintained at high frequencies, but device complexity increases
Solution Approach 1:
The patent uses a variable resistance element whose resistance parameter is changed based on frequency and operational mode. The multi-bit digital controller manages these parameter changes efficiently, adjusting the resistance to maintain signal swing. This parameter-based approach allows the circuit to adapt to different conditions without requiring fundamentally different circuit topologies, thus managing complexity through parameter control rather than structural complexity.
Data Source
AI summary
The present invention relates to a combiner latch circuit for generation of one phase differential signal pair or two phase differential signal pairs. The combiner latch circuit comprises an input circuit configured to select a state of the output circuit from a group of: a fourth state comprising the differential output X=1, Y=0, a fifth state comprising the differential output X=0, Y=1. The input circuit is further configured to select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state, and select the fifth state if the input A=1 and the input B=0 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fourth state.