Combination Volatile Nonvolatile Memory IC for Smart Card Applications
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Solution Overview
Problem
Current nonvolatile memory technologies, such as EEPROM, NOR-type flash, and NAND-type flash, are not fully compatible and are difficult to integrate on the same integrated circuit chip, limiting their ability to efficiently store high-density, high-security data like biometric information in smart card applications, where high program/erase cycles and compact cell sizes are required.
Innovation Solution
A combination volatile and nonvolatile memory integrated circuit is developed, incorporating SRAM, mask programmable ROM, and multiple NAND configured nonvolatile memory arrays on a single substrate, with a memory control circuit that generates necessary voltages and signals for reading, writing, and erasing, allowing for efficient addressing and data transfer between arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple nonvolatile memory technologies (EEPROM, NOR-type flash, NAND-type flash) are integrated on the same chip, then storage density and functionality are improved, but manufacturing compatibility and device complexity worsen
Solution Approach 1:
The patent combines multiple nonvolatile memory technologies (EEPROM, NOR-type flash, NAND-type flash) and volatile SRAM on a single integrated circuit substrate, creating a unified memory system that provides both high storage density and manufacturing compatibility through shared fabrication processes
Solution Approach 2:
The integrated circuit is designed to perform multiple memory functions simultaneously - storing permanent data, frequently modified data, and temporary data - using a universal substrate that supports all memory types, thereby achieving multi-functionality without sacrificing manufacturing ease
2Adaptability or versatility
If multiple nonvolatile memory technologies are integrated on the same chip, then storage functionality is improved, but device complexity increases
Solution Approach 1:
The memory system is segmented into distinct functional regions - SRAM for temporary data, EEPROM for frequently modified data, NOR-type flash for program storage, and NAND-type flash for bulk data storage - allowing each segment to be optimized independently while maintaining overall system manageability
Solution Approach 2:
A memory control circuit acts as an intermediary between the external interface and the multiple memory arrays, managing address decoding, data transfer, and operational control to simplify the complexity of interacting with multiple memory technologies
3Quantity of substance
If compact cell sizes are used to increase storage density, then storage density is improved, but manufacturing precision requirements worsen
Solution Approach 1:
Different memory technologies are employed in different regions of the chip - NOR-type flash and NAND-type flash for high-density bulk storage, EEPROM for frequently accessed data, and SRAM for temporary storage - allowing each region to be optimized for its specific function while maintaining overall manufacturing feasibility
Data Source
AI summary
A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that each array may be addressed with common addressing signals. The combination volatile and nonvolatile memory integrated circuit further has a memory control circuit in communication with external circuitry to receive address, command, and data signals. The memory control circuit interprets the address, command, and data signals, and for transfer to the volatile memory array and the nonvolatile memory arrays for reading, writing, programming, and erasing the volatile and nonvolatile memory arrays. The volatile memory array is may be a SRAM, a pseudo SRAM, or a DRAM. Any of the nonvolatile memory arrays maybe masked programmed ROM arrays, NAND configured flash memory NAND configured EEPROM.