Command Sampling Circuit with Delay Alignment for DRAM 1N Mode

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Solution Overview

Problem

Existing DRAM technologies face inefficiencies in command sampling due to transmission delays and missed data windows, particularly in high-frequency operations, leading to failures in the 1N mode.

Innovation Solution

A command sampling circuit that includes a sampling circuit and a delay circuit, which samples memory commands at two edges of a sampling clock, with a delay circuit delaying the first cycle command to ensure simultaneous decoding and address information output, reducing the need for multiple flip-flop stages and simplifying the circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple flip-flop stages are used to sample memory commands, then sampling accuracy is improved, but transmission delay increases and data windows are missed

Engineering Contradiction:

Improvesampling accuracyVSAvoidtransmission delay

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The delay circuit performs preliminary delay action on the first cycle command before it reaches the command decoding circuit. By pre-delaying the command signal to match the timing of the second cycle command, the system eliminates the need for multiple flip-flop stages while maintaining sampling accuracy and reducing transmission delay.

Inventive Principle:

Principle #10Preliminary action

2Stability of the object's composition

If multiple flip-flop stages are used to ensure simultaneous output, then output synchronization is improved, but circuit complexity increases

Engineering Contradiction:

Improveoutput synchronizationVSAvoidcircuit complexity

Core Design Contradiction:

Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The invention extracts and removes the unnecessary multiple flip-flop stages from the command sampling circuit. By using a delay circuit to achieve timing alignment instead of multiple flip-flop stages, the system maintains output synchronization while significantly reducing circuit complexity.

Inventive Principle:

Principle #2Taking out (Extraction)

3Productivity

If commands are sampled at high frequency, then productivity is improved, but transmission delays cause missed data windows

Engineering Contradiction:

Improvecommand sampling efficiencyVSAvoiddata window capture accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The invention changes the timing parameter of the first cycle command by introducing a delay circuit. This parameter adjustment ensures that even at high sampling frequencies, the delayed command arrives at the decoding circuit within the correct data window, maintaining both productivity and reliability.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250216892A1Command sampling circuit and memory

Publication Date: 2025.07.03 RUILI INTEGRATED CIRCUIT CO LTD

AI summary

The present disclosure provides a command sampling circuit and a memory. The command sampling circuit includes a sampling circuit and a delay circuit. The sampling circuit samples a memory command separately in response to a first sampling edge and a second sampling edge of a sampling clock, and outputs a first cycle command and a second cycle command; the delay circuit delays a command output at a first output end of the sampling circuit and then outputs a delayed command; a command decoding circuit receives an output clock, decodes the commands output by the sampling circuit, and outputs a current decoded result as decoding information of the memory command; an address output circuit receives the output clock and outputs, in response to the output edge, a command currently output at a second output end of the sampling circuit as address information of the memory command.