Static Storage TRIZ Cases
- Semiconductor Memory Repair Circuit Selection for Redundancy Reliability
A holding circuit enables parallel repair-circuit selection, preserving memory redundancy repair paths when circuits or wiring fail.
- Memory Write Validity Detection via Status Register Feedback
A mode register flags invalid memory writes so hosts can retransmit data or pause applications after command faults.
- Memory Repair Circuit for Adaptive Wordline Redundancy
A repair circuit switches between shared and individual wordline repair to match failed-cell patterns across memory banks.
- Memory Access Validity Signaling with Counter Feedback
Transmission and reception counters plus voltage-gated error signaling help detect invalid memory data while limiting power use.
- NAND Flash Read Reference Voltage Calibration for Lower Bit Errors
ECC-coded reference data guides read-voltage updates, adapting NAND flash reads to charge loss and inter-cell interference.
- 3D NAND Staircase and CMOS Contact Etch Consolidation
This case merges staircase and CMOS contact etches in 3D NAND to cut wafer cost and avoid liner damage.
- Vertical-Channel Semiconductor Memory for Dense Stacking and Low Leakage
Stacked cell and peripheral structures use vertical channels and interconnects to increase density, speed operations, and reduce leakage.
- Phase-Change Memory Cell Stacking With Low-Parasitic Via Structures
Vertical memory-cell integration uses through-layer vias to limit parasitic capacitance.
- Command Sampling Circuit with Delay Alignment for DRAM 1N Mode
Dual-edge sampling and pre-delay align DRAM commands for accurate 1N operation.
- Read Disturb Charge Loss Scanning for High-Temperature Memory
Periodic RDCL scans target high-risk word-line pages and fold error-heavy blocks after high-temperature read stress.
- Memory Die On-Die Testing for Faster, Finer Failure Detection
On-die processing circuitry tests memory internally, using faster clocks and analog-to-digital conversion for finer failure data.
- Memory BIST Circuit for Non-Destructive ASIL-D Testing
A register, comparator, inverter, and controller support parallel memory testing with low time overhead while preserving stored data.