Vertical-Channel Semiconductor Memory for Dense Stacking and Low Leakage
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in increasing integration density, operational speed, and yield while maintaining low electrical resistance and high current driving capability.
Innovation Solution
The semiconductor memory device incorporates a vertical channel transistor structure with a cell structure, peripheral structure, and interconnection structure stacked sequentially, featuring vertical channel transistors and capacitors, along with specific arrangements of bit lines, word lines, and transistors to enhance integration and reduce horizontal area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical channel transistors are used, then integration density is enhanced and current driving capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors, utilizing the third dimension (vertical direction) to increase integration density. The channel extends vertically through multiple insulating layers, allowing more transistors to be packed in the same horizontal area while maintaining electrical performance.
Solution Approach 2:
The vertical channel transistor is segmented into distinct functional regions including source region, drain region, and channel region, with each region having specific doping concentrations. This segmentation allows optimized electrical characteristics while managing manufacturing complexity through standardized region definitions.
2Area of stationary object
If cell structure and peripheral structure are stacked vertically, then horizontal area is reduced, but electrical resistance and connectivity challenges increase
Solution Approach 1:
The cell structure and peripheral structure are nested vertically, with the cell structure positioned above the peripheral structure. Connection pads are strategically positioned at different vertical levels to establish electrical connections between the stacked structures, reducing horizontal area while managing electrical resistance through optimized vertical interconnections.
Solution Approach 2:
Connection pads serve as intermediaries between the cell structure and peripheral structure, facilitating electrical connections across the vertical interface. These pads are positioned to minimize resistance and ensure reliable signal transmission between the stacked functional blocks.
3Speed
If vertical channel transistors with segmented doping are used, then operational speed is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
Different regions of the vertical channel transistor are doped with different concentrations to optimize local electrical properties. The source and drain regions have higher doping concentrations for efficient charge injection, while the channel region has lower doping for controlled conduction, enhancing operational speed while managing manufacturing precision through well-defined regional specifications.
Data Source
AI summary
A semiconductor memory device is provided. The device includes a cell structure, a peripheral structure, and an interconnection structure sequentially stacked on a support substrate, in which the cell structure includes lower electrodes, a dielectric layer and an upper electrode with the dielectric layer and the upper electrode sequentially covering the lower electrodes, the peripheral structure includes a peripheral substrate and transistors disposed on a front surface of the peripheral substrate, and an upper surface of the upper electrode faces a back surface of the peripheral substrate.