Memory Access Validity Signaling with Counter Feedback

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Solution Overview

Problem

Existing memory systems face challenges in accurately determining valid memory access operations, leading to increased failure rates due to the inability to distinguish between valid and invalid data, particularly in critical applications like autonomous vehicles, where packaging changes can exacerbate these issues.

Innovation Solution

Implementing enhanced signaling techniques, such as transmission-side and reception-side counters, and coupling error management channels with voltage sources based on clock signals to indicate valid operations in real-time, thereby reducing power consumption and improving data reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional memory access validation methods are used, then device complexity is reduced, but reliability deteriorates due to inability to distinguish valid and invalid data

Engineering Contradiction:
Improvedata validity determination accuracyVSAvoidsignaling mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a valid operation signal as an intermediary element that mediates between the memory device and host device. This signal acts as a mediator to convey validity information without requiring complex validation protocols, thus improving reliability while maintaining relatively simple device architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The valid operation signal implements a feedback mechanism where the memory device provides validity information back to the host device about memory access operations. This feedback loop enables the host to distinguish valid from invalid data without adding significant complexity to the overall system.

Inventive Principle:
Principle #23Feedback

2Reliability

If enhanced signaling techniques with counters are implemented, then reliability is improved through accurate valid operation indication, but device complexity increases

Engineering Contradiction:
Improvevalid operation indication accuracyVSAvoidcounter management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The counter mechanism operates autonomously within the memory device, automatically incrementing or decrementing based on valid operation detection. This self-service approach reduces the need for complex external validation logic, improving reliability while keeping the counter management relatively simple and localized.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The counters are pre-configured and managed in advance to track valid operations before data transfer occurs. This preliminary setup allows for accurate validity determination during operation without requiring complex real-time validation logic.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If error management channels are continuously active, then reliability is improved through constant monitoring, but power consumption increases

Engineering Contradiction:
Improveerror detection capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The error management channel operates periodically rather than continuously, activating only when valid operation signals are received or when monitoring is required. This periodic operation maintains error detection capability while significantly reducing power consumption compared to continuous monitoring.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The error management channel's operational state is dynamic, transitioning between active and inactive states based on system conditions. This dynamic behavior allows the system to maintain reliability when needed while conserving power during normal operation, resolving the contradiction between constant monitoring and power consumption.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12354691B2Indicating valid memory access operations
Publication Date: 2025.07.08 MICRON TECHNOLOGY INC
  • US12354691B2 patent drawing
  • US12354691B2 patent drawing
  • US12354691B2 patent drawing

AI summary

Methods, systems, and devices for memory operations are described. A command may be received by a memory device and from a device. Both the device and the memory device may maintain counters of valid operations. A request for a value associated with a counter at the memory device may be received from the device. Based on receiving the request, a value of the counter may be transmitted to the device. The values of the counters may be compared to determine whether invalid data has been obtained by the device. Also, a pin associated with communicating error correction information may be coupled with a voltage source based on receiving a signal. The pin may remain coupled with the voltage source until a command is processed or an end of the signal. Whether the pin is coupled with the voltage source may indicate a validity of associated data.