Memory Die On-Die Testing for Faster, Finer Failure Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory die evaluation techniques face limitations in terms of the types of operations that can be performed, duration and speed of evaluations, quantity of memory dies that can be evaluated concurrently, and granularity of information communicated, which restricts the flexibility and efficiency of manufacturing processes.
Innovation Solution
Incorporating on-die processing circuitry in memory dies that enables evaluations to be performed internally, allowing for finer granularity of failure detection, faster operation speeds, and enhanced communication of evaluation data, including analog-to-digital conversion capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If external evaluation devices are used to test memory dies, then device complexity is reduced, but evaluation speed and throughput are limited by communication interfaces
Solution Approach 1:
The memory die includes an evaluation processor and test circuitry that enables the die itself to perform self-evaluation without requiring complex external testing equipment. The die can autonomously execute test sequences, manage evaluation operations, and communicate results through standard interfaces, thereby increasing evaluation speed while avoiding the complexity of sophisticated external evaluation devices.
Solution Approach 2:
The evaluation functionality is segmented into separate functional blocks within the memory die, including an evaluation processor, test circuitry, and communication interfaces. This segmentation allows the evaluation functions to be isolated and executed independently, enabling parallel testing operations and improving throughput without requiring a monolithic complex external system.
2Measurement precision
If detailed evaluation operations are performed to achieve fine granularity failure detection, then measurement precision is improved, but evaluation time and throughput are reduced
Solution Approach 1:
The evaluation processor continuously executes test sequences and monitors memory cell operations without interruption, maintaining productive evaluation actions throughout the testing process. This continuous operation enables detailed failure detection at fine granularity while preserving high throughput by eliminating idle periods and ensuring uninterrupted evaluation of multiple memory cells.
Solution Approach 2:
Test patterns and evaluation sequences are pre-configured in the evaluation processor before actual testing begins. This preliminary preparation of test data and evaluation protocols enables rapid execution of detailed failure detection operations without time-consuming on-the-fly configuration, thereby achieving high measurement precision without sacrificing throughput.
3Productivity
If multiple memory dies are evaluated concurrently to increase productivity, then throughput is improved, but communication overhead and coordination complexity increase
Solution Approach 1:
Each memory die includes its own evaluation processor and test circuitry, enabling autonomous self-evaluation without requiring centralized coordination. Multiple dies can simultaneously execute evaluation operations independently, increasing throughput while avoiding the coordination complexity that would arise from centralized management of multiple tested devices.
Solution Approach 2:
The evaluation system is segmented into independent evaluation units within each memory die, with each unit managing its own testing operations. This segmentation allows parallel evaluation of multiple dies without creating complex inter-device coordination requirements, as each die operates autonomously with its own evaluation processor and test sequences.
4Productivity
If evaluation operations are performed at faster speeds, then productivity is improved, but the types of operations that can be performed are limited
Solution Approach 1:
The evaluation processor dynamically adjusts evaluation operation types and sequences based on real-time testing requirements and memory cell conditions. This dynamic adaptability enables the system to perform diverse evaluation operations at high speeds by selecting appropriate test sequences and adjusting parameters on-the-fly, rather than being constrained to a fixed set of operations.
Solution Approach 2:
The evaluation processor is designed as a universal platform capable of executing multiple types of evaluation operations through a single integrated architecture. By incorporating versatile test circuitry and programmable evaluation logic, the system can perform various operation types (read, write, stress tests, etc.) at high speeds without requiring separate dedicated hardware for each operation type.
Data Source
AI summary
Methods, systems, and devices for on-die testing for a memory device are described. In some examples, a memory die may include processing circuitry configured to perform evaluations of the memory die based on commands or instructions received from an external device. The processing circuitry may be configured to detect failures of the memory die and transmit related indications to the external device based on the on-die detection. In some examples, the processing circuitry may be configured to communicate failure information at a finer granularity than information associated with expected or nominal behavior. Additionally or alternatively, the processing circuitry may be configured to perform operations according to an internally-generated clock signal that operates at a faster rate or speed than a clock signal from the external device. In some examples, the processing circuitry may include an analog-to-digital conversion capability for digital communication of analog characteristics internal to the memory die.