Memory Write Validity Detection via Status Register Feedback

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Solution Overview

Problem

Memory devices experience faults in receiving or executing commands, leading to data loss and failure to satisfy functional safety constraints, which existing ECC schemes like host inline ECC and link ECC are unable to detect.

Innovation Solution

Implementing a memory system that sets a flag or signals the status of a write operation via a mode register or pin to indicate its validity, allowing the host system to take corrective actions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing ECC schemes (host inline ECC and link ECC) are used to detect errors, then data transmission reliability is improved, but command execution faults cannot be detected

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidcommand execution fault detection
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent introduces an intermediary mechanism (status register or dedicated signal line) that mediates between the memory device and host system. This intermediary carries write operation status information from the memory device to the host system, enabling the host to detect command execution faults without requiring complex modifications to existing ECC schemes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a feedback mechanism where the memory device provides status information about write operations back to the host system. This feedback loop allows the host system to determine whether write operations were successfully executed or if faults occurred, enabling corrective actions to be taken.

Inventive Principle:
Principle #23Feedback

2Reliability

If the memory system implements comprehensive fault detection, then functional safety requirements are met, but system complexity increases

Engineering Contradiction:
Improvefunctional safety complianceVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the fault detection function from the complex memory system into a separate, dedicated mechanism (status register or signal line). This extraction allows comprehensive fault detection to be implemented without significantly increasing the overall system complexity, as the detection logic is isolated and standardized.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The status register or signal line mechanism serves multiple functions: it indicates write operation completion, signals fault conditions, and provides information for corrective actions. This multi-functionality reduces the need for separate dedicated components for each function, thereby limiting complexity increase.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If the host system continuously monitors write operations, then data loss is reduced, but processing time increases

Engineering Contradiction:
Improvedata loss preventionVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by having the memory device prepare and make available write operation status information in advance (in status registers or through signal lines) before the host system needs to check it. This allows the host system to quickly query status without waiting for operation completion, reducing monitoring time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces continuous active monitoring with a passive status query mechanism. Instead of continuously checking operation status (which would consume processing time), the host system can quickly query the status register or check signal lines only when needed, substituting continuous mechanical monitoring with efficient status checking.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250226043A1Valid write operation detection for memory devices
Publication Date: 2025.07.10 MICRON TECHNOLOGY INC
  • US20250226043A1 patent drawing
  • US20250226043A1 patent drawing
  • US20250226043A1 patent drawing

AI summary

Methods, systems, and devices for valid write operation detection for memory devices are described. The described techniques provide for a memory system to set a flag in accordance with a status of an access operation. The memory system may receive a command to write data and may adjust a value of a mode register based on whether a write operation is valid. In some examples, the memory system may set the mode register value after successfully receiving, decoding, or completing the write command. In some other examples, if the memory system experiences a fault in receiving, decoding, or executing the write command, the memory system may refrain from setting the mode register value. A host device may poll the mode register to identify the validity of the write operation, and may perform one or more corrective actions if the write operation is invalid.