Phase-Change Memory Cell Stacking With Low-Parasitic Via Structures

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

There is a need to improve electronic chips with memory circuits based on phase-change materials by enhancing the integration and performance of memory cells while minimizing parasitic capacitance and reducing material contamination risks.

Innovation Solution

The design includes a semiconductor substrate with selection transistors, multiple interconnection stacks with specific insulating layers and conductive vias, and memory cells in a third insulating layer, utilizing a conductive via that extends through the entire height to couple conductive tracks and vias, with a phase-change material resistive element and a distinct, high-dielectric constant layer to reduce parasitic capacitance and contamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory cells are integrated in the third insulating layer, then memory cell integration is enhanced, but parasitic capacitance increases

Engineering Contradiction:

Improvememory cell integrationVSAvoidparasitic capacitance

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

A dedicated via layer (via 70) extending through the entire height of the third insulating layer serves as an intermediary element to couple conductive tracks and vias between first and second interconnection stacks. This intermediary structure provides controlled electrical connections while minimizing parasitic capacitance through optimized via geometry and positioning.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent utilizes vertical stacking of multiple interconnection stacks (first and second stacks) separated by the third insulating layer, transitioning from planar to three-dimensional integration. This dimensional approach allows memory cells to be integrated in the vertical dimension while maintaining electrical isolation through the insulating layer, thereby reducing parasitic capacitance between adjacent conductive elements.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple interconnection stacks are used, then memory cell integration is enhanced, but material contamination risks increase

Engineering Contradiction:

Improvememory cell integrationVSAvoidmaterial contamination

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The interconnection structure is segmented into multiple independent stacks (first and second interconnection stacks) separated by the third insulating layer. This segmentation isolates different interconnection levels, preventing material contamination between stacks while enabling enhanced memory cell integration through the multi-stack architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The third insulating layer is positioned beforehand between the first and second interconnection stacks to provide a protective barrier against material contamination. This preventive measure cushions against potential contamination during manufacturing processes while allowing the stacks to be integrated closely for improved productivity.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If conductive vias extend through the entire height of the third insulating layer, then electrical coupling is improved, but manufacturing complexity increases

Engineering Contradiction:

Improveelectrical couplingVSAvoidvia structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The via structure (via 70) extending through the entire height of the third insulating layer serves multiple functions simultaneously: it provides electrical coupling between conductive tracks and vias of different interconnection stacks, acts as a structural support element, and defines the vertical alignment between stacking levels. This multi-functionality improves electrical coupling reliability while avoiding the need for additional separate structures that would increase manufacturing complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This structure enhances memory cell integration, reduces parasitic capacitance, and minimizes material contamination, maintaining compatibility with existing manufacturing methods and logic parts.

Implementation Method 1

A phase-change material is a material having the ability to change crystalline state under the effect of heat, and more specifically to switch between a crystalline state and an amorphous state

Methodology Applied

Scientific EffectPhase change: Phase Change

Implementation Method 2

a distinct, high-dielectric constant layer to reduce parasitic capacitance

Methodology Applied

Scientific EffectDielectric: Dielectric

Data Source

PatentUS20250218469A1Electronic device

Publication Date: 2025.07.03 STMICROELECTRONICS (CROLLES 2) SAS

AI summary

An electronic device includes—a semiconductor substrate having selection transistors arranged therein and a first interconnection stack including at least one level including first and second insulating layers having conductive tracks and first conductive vias defined therein. The electronic device includes a third insulating layer on the first stack and a second interconnection stack including at least one level including first and second insulating layers. The electronic device includes a plurality of memory cells arranged in the third insulating layer and at least one second conductive via extending through the entire height of the third insulating layer.