Common Body Bias Region Layout for Compact NMOS Integration
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Solution Overview
Problem
As semiconductor devices become more integrated, the available area for forming semiconductor elements decreases, leading to increased wiring complexity and area requirements due to separate body bias regions for transistors, which complicates manufacturing and increases the size of the device.
Innovation Solution
A semiconductor device design that incorporates a common body bias region between two NMOS transistors, contacting both the P-well region and the substrate, allowing for simultaneous bias voltage provision to both transistors, thereby reducing the overall area and complexity by sharing a single body bias terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate body bias regions are provided for each transistor, then each transistor can be independently biased, but the device area increases and wiring complexity increases
Solution Approach 1:
The patent combines separate body bias regions into a single common body bias region that serves multiple transistors (first NMOS and second NMOS). This common body bias region is formed in the P-well and shares the same bias voltage terminal, eliminating the need for separate bias regions and reducing overall device area while maintaining bias control functionality.
Solution Approach 2:
The common body bias region is designed to serve multiple functions: it provides bias control for both the first NMOS transistor in the P-well and the second NMOS transistor on the substrate simultaneously. This multi-functional design allows a single structure to replace what would traditionally require multiple separate structures.
2Reliability
If separate body bias regions are provided for each transistor, then each transistor can be independently biased, but wiring complexity increases
Solution Approach 1:
The patent merges multiple bias voltage terminals into a single common bias voltage terminal that connects to the common body bias region. This consolidation reduces the number of wiring paths and terminals required, simplifying the overall wiring structure while maintaining the ability to provide bias control to multiple transistors.
3Ease of manufacture
If separate body bias regions are provided for each transistor, then manufacturing can be simplified, but the device area increases
Solution Approach 1:
The common body bias region is formed using a unified manufacturing process that creates a single doped region in the P-well, rather than requiring multiple separate doping steps and patterning operations for individual bias regions. This merged structure reduces manufacturing steps while occupying less area than multiple separate regions would require.
Data Source
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AI summary
A semiconductor device includes a substrate (PSUB), a P-well region (PW), a first N-type metal oxide semiconductor (NMOS) transistor (NM1) provided in the P-well region, a second NMOS transistor (NM2) provided on the substrate, and a common body bias region (JCB) provided between the first NMOS transistor and the second NMOS transistor and contacting both the P-well region and the substrate.