Common Electrode Layout for Stray Capacitance Reduction in Display Panels
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Solution Overview
Problem
Conventional liquid crystal display devices experience signal distortion due to stray capacitance generated when common electrodes overlap with gate lines and data lines, affecting display quality.
Innovation Solution
The display panel design includes crisscrossed gate and data lines defining pixel regions with pixel electrodes, where common electrodes are arranged to avoid overlap with gate and data lines, using strip-shaped or blocky electrodes connected via narrow first and second connection electrodes to reduce stray capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If common electrodes are arranged to overlap with gate lines and data lines, then the electrode coverage area is increased, but stray capacitance is generated causing signal distortion
Solution Approach 1:
The patent extracts and removes the overlapping portion of common electrodes that causes stray capacitance with gate lines and data lines. By designing the common electrode pattern to avoid overlap with the signal transmission lines, the harmful stray capacitance is eliminated while maintaining the essential coverage area for electric field formation.
Solution Approach 2:
The patent applies local quality by creating different spatial relationships between common electrodes and signal lines in different regions. The common electrode pattern is locally optimized to avoid overlap with gate lines and data lines in areas where signal transmission occurs, while maintaining coverage in regions where electric field formation is the primary function.
2Object-generated harmful factors
If common electrodes are designed as strip-shaped arranged between gate lines, then stray capacitance with gate lines is reduced, but connection complexity increases
Solution Approach 1:
The patent segments the common electrode into multiple strip-shaped sections arranged between adjacent gate lines. Each strip corresponds to a specific row of pixel electrodes and is separated from other strips by gaps aligned with the gate lines. This segmentation reduces stray capacitance while the systematic arrangement keeps connection complexity manageable.
Solution Approach 2:
The patent introduces connection electrodes as intermediary elements that bridge the strip-shaped common electrodes to the signal lines. These connection electrodes are strategically positioned and dimensioned to provide electrical connection while minimizing overlap and stray capacitance, acting as mediators between the common electrode structure and the signal transmission lines.
3Object-generated harmful factors
If connection electrodes are made narrow to reduce overlap, then stray capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the dimensional parameters of connection electrodes, specifically controlling their width to be less than 1/4 of the adjacent pixel electrode length. This parameter change reduces the overlap area and stray capacitance while maintaining manufacturability. The systematic dimensional relationships provide clear fabrication guidelines that balance performance and manufacturing capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces stray capacitance, improving signal transmission and display quality by minimizing overlap between common electrodes and gate/data lines, enhancing the overall performance of the liquid crystal display.
Implementation Method 1
an electric field is formed between the common electrode and the pixel electrode to drive the liquid crystal to display
Implementation Method 2
liquid crystal material is encapsulated between the array substrate and the opposing substrate
Data Source
AI summary
A display panel comprises a base substrate and a plurality of gate lines and data lines arranged on the base substrate. The gate lines and the data lines are crisscrossed to define a plurality of pixel regions. The display panel further comprises pixel electrodes arranged within the pixel regions and common electrodes arranged in opposite to the pixel electrodes, wherein an orthographic projection of the common electrodes on the substrate is not overlapped with an orthographic projection of the gate lines on the substrate, and/or the orthographic projection of the common electrodes on the substrate is not overlapped with an orthographic projection of the data lines on the substrate.