Common Element Pixel Architecture Readout Speed

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Solution Overview

Problem

Conventional common element pixel architecture (CEPA) systems inhibit readout speed as they share a single column line, requiring sequential readout of pixels in each row/group, which limits the overall speed of the imager.

Innovation Solution

Configuring pixel groups to share readout circuitry and alternately output pixel values over multiple column lines, allowing simultaneous readout of multiple rows/groups of pixels, thereby increasing readout speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If pixels are configured to share a single column line in conventional CEPA systems, then hardware complexity is reduced, but readout speed deteriorates due to sequential readout requirement

Engineering Contradiction:
Improvehardware complexityVSAvoidreadout speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent divides the pixel array into multiple pixel groups, where each group shares readout circuitry but has its own dedicated column line. This segmentation allows parallel readout of multiple pixel groups simultaneously, resolving the contradiction by maintaining hardware sharing benefits while enabling faster parallel readout through column line segmentation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-column sequential readout architecture to a multi-column parallel readout architecture. By adding the column line dimension, multiple pixel groups can be read out simultaneously across different column lines, thereby increasing readout speed without proportionally increasing overall hardware complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If multiple column lines are used to readout pixel groups simultaneously, then readout speed is improved, but device complexity increases

Engineering Contradiction:
Improvereadout speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges the readout circuitry functionality across multiple pixel groups, allowing shared readout circuits to serve multiple groups. This merging approach enables parallel readout through multiple column lines while avoiding proportional increases in overall device complexity, as the readout circuitry is efficiently shared rather than duplicated

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9001240B2Common element pixel architecture (CEPA) for fast speed readout
Publication Date: 2015.04.07 SEMICON COMPONENTS IND LLC
  • US9001240B2 patent drawing
  • US9001240B2 patent drawing
  • US9001240B2 patent drawing

AI summary

The present invention relates to a common element pixel architecture (CEPA) imager. The CEPA includes a first column of pixels and a second column of pixels. The CEPA also includes a first column line and a second column line. A first group of pixels is arranged including pixels from the first column and the second column coupled to the first column line. A second group of pixels is arranged including other pixels from the first column and the second column coupled to the second column line.