Communication Circuitry Integrity Assessment via Reduced Voltage Testing
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Solution Overview
Problem
Communication circuitry in data bus applications, such as CAN bus systems, is susceptible to manufacturing defects and degradation over time, making it challenging to assess integrity, particularly in wire harnesses with weak connections that may not be detectable at standard signal levels, leading to potential communication failures.
Innovation Solution
A method and apparatus that transmit a test signal with a reduced differential voltage relative to the design differential signal to expose and assess potential issues in connecting circuitry, allowing for the detection of faulty connections by sensing the state of the bus after transmitting an initial test bit sequence, and generating an output indicative of potentially faulty circuit connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard signal levels are used for communication, then normal data transmission is maintained, but integrity issues in wire harnesses and connectors remain undetected
Solution Approach 1:
The system performs integrity assessment by transmitting test signals with reduced differential voltage before normal communication occurs. This preliminary action detects potential failures in wire harnesses and connectors while they still function at normal signal levels, allowing proactive maintenance before actual communication failures occur.
Solution Approach 2:
The system changes the voltage parameter of test signals to a reduced level (below normal operating voltage) specifically for integrity assessment. This parameter change enables detection of connection weaknesses that would not be apparent at standard communication signal levels, as attenuated signals reveal marginal connections before they cause failures.
2Measurement precision
If reduced differential voltage test signals are transmitted, then potential integrity issues in connecting circuitry are exposed, but the test signal may not be detectable by all circuit nodes
Solution Approach 1:
The system transmits test signals at reduced voltage levels that are intentionally below the threshold required for all circuit nodes to reliably detect them. This partial action approach deliberately creates conditions where some nodes may fail to detect the signal, which itself becomes diagnostic information about the health of connection pathways and node responsiveness.
Solution Approach 2:
The system monitors whether circuit nodes respond to test signals and uses this feedback to assess integrity. When nodes fail to respond to reduced-voltage test signals but would respond to normal signals, this feedback indicates degraded connections or node issues that require attention before they cause actual communication failures.
3Reliability
If integrity assessment is performed continuously, then potential failures are detected early, but communication protocol timing and bus occupancy increase
Solution Approach 1:
The system performs integrity assessment periodically rather than continuously, scheduling test signal transmissions at intervals that balance early failure detection with minimal impact on normal communication. This periodic approach ensures that the bus is occupied with testing only when necessary, maintaining productivity while still providing timely integrity monitoring.
Solution Approach 2:
The system rapidly transmits test signals and quickly processes responses to minimize bus occupancy time. By rushing through the integrity assessment process efficiently, the system detects potential failures early without significantly impacting communication throughput or occupying the bus for extended periods.
Data Source
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AI summary
Aspects of the present disclosure are directed to assessing integrity of communications circuitry. As may be implemented in accordance with one or more embodiments, a circuit node carries out a test protocol utilizing characteristics of a communication protocol to detect potential integrity issues. An initial test bit sequence is transmitted to circuit nodes connected to signal lines of a bus, by providing a test voltage across the signal lines that is less than an operating voltage potential of the bus. An ensuing state of the bus is sensed, and integrity of the bus or of circuitry connected to the bus is assessed based on the sensed state of the bus and on a state that the bus is expected to be in after transmission of the initial test bit sequence, which is used as an indication of whether all of the circuit nodes received the initial test bit sequence.