Bit-Order In-Memory Computation for Compact Multiply-Add Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing technologies face challenges in efficiently executing multiply-add operations in neural-like networks due to the need for a simple hardware circuit capable of performing these operations quickly, particularly in in-memory computation devices.
Innovation Solution
An in-memory computation device and method that utilizes a memory cell array with a memory cell block storing multiple weight values, an input buffer transmitting input signals to bit lines, and a sense amplifier performing multiplication and addition operations based on bit orders to achieve multiply-add operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional separate computation and memory architecture is used, then computation speed can be maintained, but circuit area increases and computation efficiency decreases
Solution Approach 1:
The patent merges the memory array and computation circuitry into a single integrated structure. Memory cells are directly coupled to bit lines that serve as computation elements, allowing multiply-add operations to be performed within the memory array itself. This eliminates the need for separate computation units and reduces overall circuit area while improving computation efficiency.
Solution Approach 2:
The memory cells serve multiple functions: they store weight values and simultaneously perform multiplication operations. The bit lines serve dual purposes as both memory access lines and computation elements for accumulation. This multi-functionality reduces the need for dedicated computation hardware and decreases circuit area.
2Area of stationary object
If high-density memory cells are used for in-memory computation, then circuit area is reduced, but operation speed may be compromised
Solution Approach 1:
The patent pre-arranges weight values in memory cells and configures the memory array structure before computation. Word lines are pre-configured to activate specific rows, and bit lines are pre-positioned to receive and accumulate multiplication results. This preliminary setup enables high-speed computation without sacrificing density.
Solution Approach 2:
The computation process continuously activates multiple word lines simultaneously to perform parallel multiplication operations. The bit lines continuously accumulate results from multiple memory cells in parallel, maintaining high operation speed while utilizing the full capacity of the high-density memory array.
3Measurement precision
If multiple bit operations are performed sequentially, then computation accuracy is maintained, but computation time increases
Solution Approach 1:
The patent segments the computation into parallel operations across multiple bit lines, where each bit line handles a specific portion of the multiply-add operation. This segmentation allows simultaneous processing of multiple bits while maintaining computational accuracy through structured accumulation, significantly reducing computation time compared to sequential processing.
Solution Approach 2:
The patent transitions from sequential single-bit processing to parallel multi-bit processing by utilizing the spatial dimension of the memory array. Multiple word lines and bit lines operate simultaneously in parallel, effectively adding a temporal dimension to the computation process and reducing overall computation time while maintaining accuracy through proper result accumulation.
Data Source
AI summary
An in-memory computation device and computation method are provided. The in-memory computation method includes: providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values; respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer; providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.