Compact FLL Architecture With Discrete-Time Integrator
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional frequency-locked loops (FLLs) occupy a large area due to digital-to-analog conversion circuitry requirements for fine resolution and wide frequency range, and they experience significant jitter and area consumption.
Innovation Solution
The implementation of a frequency-locked loop with a digital-to-analog converter (DAC) and a discrete-time integrator, allowing for a smaller DAC with reduced bit resolution and the use of a supplemental oscillator to maintain frequency during reference clock disconnection, utilizing a switched-capacitor integrator for control voltage generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital-to-analog conversion circuitry is used to achieve fine resolution and wide frequency range, then frequency control precision is improved, but area occupied by the FLL increases
Solution Approach 1:
The frequency control is segmented into two independent domains: a digital domain for coarse frequency adjustment (providing wide frequency range) and an analog domain for fine frequency adjustment (providing fine resolution). This segmentation allows each domain to use optimized circuitry appropriate to its function, reducing the total area compared to a purely digital high-resolution solution.
Solution Approach 2:
An analog integrator is introduced as an intermediary component between the digital coarse control and the VCO. This integrator converts the digital control signal to an analog control voltage, enabling fine frequency adjustment without requiring a high-resolution digital-to-analog converter, thus reducing the overall circuit area while maintaining frequency control precision.
2Reliability
If conventional FLL architecture is used, then frequency locking function is achieved, but jitter increases
Solution Approach 1:
The analog integrator serves as a mediator that smooths the control signal to the VCO by filtering out high-frequency digital switching artifacts. This integration process inherently reduces jitter in the output frequency while maintaining the frequency locking function, as the integrator averages out rapid fluctuations in the control signal.
Solution Approach 2:
The FLL employs feedback mechanisms where the actual VCO frequency is continuously monitored and compared with the target frequency. The error signal is processed through the analog integrator which provides smooth correction, reducing jitter while maintaining accurate frequency locking. The feedback loop ensures that frequency deviations are corrected without introducing additional jitter.
3Measurement precision
If high-resolution digital-to-analog converter is used, then frequency resolution is improved, but device complexity increases
Solution Approach 1:
The frequency control resolution is segmented between digital coarse steps and analog fine tuning. The digital portion uses low-resolution control signals that are simple to generate and process, while the analog integrator provides continuous fine adjustment. This segmentation avoids the need for complex high-resolution digital-to-analog converters, reducing overall device complexity while maintaining fine frequency resolution.
Solution Approach 2:
The patent replaces a complex digital high-resolution digital-to-analog converter with a simpler analog integrator circuit. The integrator uses basic analog components (resistors, capacitors, operational amplifiers) to provide fine frequency control, substituting a complex digital system with a simpler analog system that achieves the same functional goal with reduced complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the area occupied by the FLL and decreases low-frequency jitter, enabling a more compact and stable frequency-locked loop with preserved frequency during reference clock disconnection and quick reacquisition of frequency lock upon reconnection.
Implementation Method 1
a discrete-time integrator having an input coupled to an output of the DAC, and a voltage-controlled oscillator (VCO) having a control input coupled to an output of the discrete-time integrator
Implementation Method 2
utilizing a switched-capacitor integrator for control voltage generation
Implementation Method 3
a voltage-controlled oscillator (VCO) having a control input coupled to an output of the discrete-time integrator
Data Source
AI summary
Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.