Compact Gain Cell With Shared Read-Write Bitline for Dense Memory Arrays
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Solution Overview
Problem
Modern integrated circuits face significant memory bottlenecks due to high latency and power costs of off-chip DRAM access, with SRAM scaling difficulties and eDRAM reliability issues, limiting performance and efficiency.
Innovation Solution
A gain cell design using a single bitline for both read and write operations, combined with non-planar transistors, reduces area requirements and enhances memory density by sharing routing tracks, thereby increasing the capacity of memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM is used for embedded memory to ensure reliability and logic compatibility, then memory reliability and ease of operation are improved, but memory density and area efficiency deteriorate due to large bitcell size
Solution Approach 1:
The patent merges the read and write bitlines into a single shared bitline for the gain cell. This consolidation reduces the number of interconnect lines required per memory cell, directly decreasing the bitcell area while maintaining both read and write functionality through time-multiplexed operation controlled by word line signals.
Solution Approach 2:
The single bitline in the gain cell serves multiple functions: it acts as both the read bitline and write bitline depending on the operation mode. The bitline is universally used for data input during write operations and data output during read operations, eliminating the need for separate dedicated lines and reducing overall memory array area.
2Area of stationary object
If eDRAM is used to increase memory density, then area efficiency is improved, but manufacturing complexity and reliability worsen due to additional process steps and scaling issues
Solution Approach 1:
The gain cell is constructed entirely from standard logic transistors using the same CMOS fabrication process as the surrounding logic circuitry. This homogeneous approach eliminates the need for specialized eDRAM process steps such as deep trench isolation or capacitor formation, allowing memory to be manufactured alongside logic in standard CMOS processes and enabling seamless scaling with technology nodes.
3Ease of operation
If separate read and write bitlines are used in gain cells, then ease of operation is improved, but memory density deteriorates due to increased routing track requirements
Solution Approach 1:
The patent merges the read and write bitlines into a single shared bitline for the gain cell. This consolidation reduces the number of interconnect lines required per memory cell, directly decreasing the bitcell area while maintaining both read and write functionality through time-multiplexed operation controlled by word line signals.
Solution Approach 2:
The single bitline operates in periodic time-multiplexed mode, alternating between write operations and read operations based on word line activation. During write operations, the bitline receives data to be stored; during read operations, the bitline outputs stored data. This periodic switching enables one physical line to perform the functions of two separate lines, reducing area while maintaining operational ease.
Data Source
AI summary
A gain cell for storing a data level includes a write element and a read element. The write element is connected to a write word line (WWL) and a bit line (BL), and is configured to write a logic level from the BL to a storage node of the gain cell when a write operation is triggered on the WWL. The write element includes at least one transistor. The read element is connected to a read word line (RWL) and the bit line (BL), and is configured to read a logic level from the storage node to the BL when a read operation is triggered on the RWL. The read element includes at least one transistor.