Compact Network Processor Using Dual-Port BRAM for PLD Resource Conservation

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Solution Overview

Problem

Network processors are typically complex and large, making them inefficient for implementation on programmable logic devices (PLDs) where resource conservation is essential.

Innovation Solution

A network processor architecture utilizing dual port block random access memory (BRAM) and a coordination processor, allowing for efficient packet processing, data width conversion, and header manipulation on an integrated circuit with programmable logic and interconnects, enabling concurrent operations and minimal latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a standard network processor architecture is used, then packet processing capability is achieved, but device size and complexity increase significantly

Engineering Contradiction:

Improvepacket processing capabilityVSAvoidnetwork processor size

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The network processor is segmented into distinct functional units: an ingress unit with dual-port BRAM for packet reception and buffering, an egress unit with dual-port BRAM for packet transmission and buffering, and a coordination processor for control operations. This segmentation allows each unit to be optimized independently and implemented efficiently on PLD resources.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The dual-port block RAM is used for multiple purposes: buffering incoming packets, buffering outgoing packets, and enabling concurrent read/write operations. The coordination processor handles multiple control functions including packet routing, buffer management, and data width conversion, reducing the need for separate dedicated circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If multiple CPU's are used in parallel configuration, then network processing efficiency is improved, but device complexity and resource consumption increase

Engineering Contradiction:

Improvenetwork processing efficiencyVSAvoidmulti-CPU architecture

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The dual-port BRAM acts as an intermediary buffer between the ingress unit and egress unit, enabling concurrent packet processing without requiring multiple full-featured CPUs. The coordination processor manages this intermediary buffer, allowing efficient parallel operations with reduced complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If data width conversion is implemented, then compatibility with different interfaces is improved, but device complexity increases

Engineering Contradiction:

Improveinterface compatibilityVSAvoiddata width conversion logic

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The dual-port BRAM is configured with different data widths on its two ports: one port is configured for network interface data width (e.g., 64 bits for Ethernet) and the other port is configured for processor interface data width (e.g., 32 bits). This parameter change approach enables automatic data width conversion without additional conversion logic, as the BRAM internally handles the width adaptation.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7590137B1Parameterizable compact network processor for low-level communication with an integrated circuit

Publication Date: 2009.09.15 XILINX INC

AI summary

A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.