Probabilistic logic circuits replace high-precision arithmetic to sample conditional distributions faster with fewer processing resources.
Programmable blocks let a universal circuit emulate hidden functions in secure two-party evaluation while disclosing only circuit size.
Uses a Hadamard-based measurement matrix to capture essential signal information with fewer measurements and built-in compression.
Non-uniform memory sub-arrays cut emulator data storage needs while supporting 25-37.5% more instructions per emulation cycle.
Generic FPGA solver logic runs different system models in real time, cutting reconfiguration effort and simulation turnaround time.