Emulation Engine Memory Layout for More Instructions Per Cycle
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Solution Overview
Problem
Hardware emulators face inefficiencies and significant cost increases due to the need for larger data array memory as the number of instructions processed per emulation cycle increases, making it challenging to keep pace with the growing complexity of integrated circuits.
Innovation Solution
The implementation of a data array with sub-arrays of varying sizes, where the size of each sub-array is determined by the probability of being accessed during future emulation steps, allows for more efficient storage and access of processor outputs, reducing the overall memory requirements without compromising emulation cycle performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of instructions processed per emulation cycle is increased, then the productivity of the emulation engine is improved, but the size of the data array must increase significantly
Solution Approach 1:
The data array is divided into multiple sub-arrays, each storing data for a specific time window (e.g., current cycle, previous cycle, two cycles ago). This segmentation allows the system to access only the necessary historical data for each instruction, reducing the total memory size required while supporting multiple instructions per cycle.
Solution Approach 2:
Different sub-arrays are allocated based on local access patterns and probability of use. Sub-arrays are configured with different depths according to how frequently data from different time windows is accessed, optimizing memory usage by providing larger storage for frequently accessed data and smaller storage for less frequently accessed data.
2Productivity
If additional data array memory is added to support more instructions per cycle, then the productivity is improved, but the cost of the hardware emulator increases significantly
Solution Approach 1:
By segmenting the data array into sub-arrays that match actual access patterns, the system achieves high productivity with minimal memory. This eliminates the need for expensive large-scale memory expansions, thereby reducing hardware costs while maintaining the ability to execute multiple instructions per cycle.
Solution Approach 2:
The system implements partial action by only storing data for the specific time windows that are actually needed for multi-instruction cycling, rather than storing all possible historical data. This partial storage approach achieves the required productivity improvement without the excessive memory investment that would be needed to store complete historical data for all possible access patterns.
3Adaptability or versatility
If the data array stores data for all possible access patterns, then the adaptability is improved, but the memory size and cost increase
Solution Approach 1:
The data array structure provides adaptability by configuring sub-arrays with different depths based on local access probability characteristics. This allows the system to adapt to different access patterns without requiring uniform large storage across all sub-arrays, achieving versatility with optimized memory utilization.
Solution Approach 2:
The system dynamically adapts to different access patterns by using probabilistic analysis to configure sub-array depths according to actual usage patterns. This dynamic configuration allows the data array to be versatile and adaptive to varying access requirements without permanently allocating excessive memory for all possible patterns.
Data Source
AI summary
A method and apparatus for a memory efficient hardware emulator. The emulator comprises a plurality of processor dusters having data within the duster is stored in at least one data array, where the at least one data array comprises a plurality of sub-arrays. The sub-arrays that are not of uniform size (e.g., the size of each sub-array is determined by the probability that a particular sub-array will be accessed by the processor during a future emulation step). For example, at least one first sub-array is equal in depth to instruction memory within a processor (i.e., equal to the number of instructions in an emulation cycle), and the remaining sub-arrays are a fractional depth of the first sub-array.