Compact SEU Latch Layout With DICE Cells and Minimum Node Spacing
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Solution Overview
Problem
Existing latch designs are highly sensitive to single-event upsets (SEUs) caused by cosmic rays and radioactive impurities, leading to data corruption and significant area penalties when attempting to implement SEU-tolerant solutions, which are not compact enough to be viable in modern integrated circuits.
Innovation Solution
The design of a compact single-event upset (SEU) latch circuit with optimized node spacing and redundancy, utilizing a clock transmission gate coupled to dual interlock storage cells (DICE) to minimize charge sharing and prevent SEU-induced errors without increasing the latch size, thereby achieving improved radiation tolerance and reduced area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SEU-tolerant latch designs (such as DICE) are used to reduce soft error rate, then reliability against single-event upsets is improved, but area overhead increases by three to four times compared to standard latches
Solution Approach 1:
The patent merges multiple storage nodes into a compact shared structure where nodes are positioned within a shared critical charge region. This allows multiple nodes to benefit from the same protective mechanism (shared reset path and clock gating) rather than requiring separate protection circuits for each node, thereby reducing overall area while maintaining SEU tolerance
Solution Approach 2:
The patent transitions from the conventional approach of increasing spatial separation between nodes (2D plane separation) to utilizing temporal control through shared clock gating and reset paths. By controlling the timing and activation of protection mechanisms across multiple nodes simultaneously, the design achieves SEU tolerance without requiring proportional area increases
2Reliability
If node spacing is increased to prevent charge sharing and SEU corruption, then single-event upset resistance is improved, but latch area increases significantly
Solution Approach 1:
The patent introduces a shared reset path and clock gating mechanism as intermediary control elements that mediate between the storage nodes and the SEU protection mechanism. These intermediaries allow compact node spacing while providing coordinated control that prevents charge sharing effects, eliminating the need for large spacing between nodes
3Area of stationary object
If redundant storage nodes are placed close together to reduce area, then area overhead is reduced, but charge sharing between nodes increases making them vulnerable to SEU
Solution Approach 1:
The patent employs dynamic clock gating control that actively manages the operational state of storage nodes based on detected conditions. By dynamically controlling when nodes are active and when they are held in a protected state, the design prevents charge sharing vulnerabilities even when nodes are physically close together, maintaining SEU resistance without requiring large spacing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SEU latch circuit achieves similar SEU performance to conventional SEU-tolerant designs while reducing area overhead by 73%, maintaining reliability with minimal on-chip real estate, and is 50 to 100 times more resilient to SEUs than standard latches.
Implementation Method 1
a first clock transmission gate coupled to the first inverter and configured to transmit an inverted first input signal to the first storage cell in response to a first phase of a clock signal
Implementation Method 2
a first inverter with an input and an output, the input of the first inverter coupled to a data input of the latch circuit
Data Source
AI summary
One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.