Compact SRAM Cell Interconnect Using Expanded Vias
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Solution Overview
Problem
The challenge in integrating SRAM cells with microprocessors is the need for additional masks and process steps due to different manufacturing requirements, leading to alignment errors, increased cell size, and high capacitance issues.
Innovation Solution
A compact SRAM cell layout that uses the same masks and process steps as the microprocessor, incorporating expanded vias and contacts to reduce alignment errors and capacitance, and employs low-resistivity metals for interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If specialized masks and process steps are used for SRAM cell manufacturing, then manufacturing precision can be maintained, but device complexity and mask alignment error risk increase
Solution Approach 1:
The patent applies universality by designing the SRAM cell to use the same masks and process steps as the microprocessor manufacturing. The memory cell is integrated into the microprocessor fabrication flow, allowing shared use of process equipment and masks for both CPU and SRAM fabrication, thereby reducing process complexity while maintaining manufacturing precision through established process control
2Reliability
If additional metal wiring layers are added to connect contacts and gates, then electrical connectivity is improved, but capacitance increases and cell size increases
Solution Approach 1:
The patent applies dimensionality change by extending the metal via vertically through multiple insulator layers to directly connect the contact to the gate. This three-dimensional via structure eliminates the need for additional planar metal wiring layers, reducing capacitance and cell area while maintaining reliable electrical connectivity through the vertical dimension
3Area of stationary object
If transistors are placed closer together to reduce cell area, then area is reduced, but risk of shorting and capacitive coupling increases
Solution Approach 1:
The extended metal via provides direct vertical connection through insulator layers, allowing transistors to be placed closer in the planar dimension while maintaining electrical isolation through the insulating layers. The via extends through multiple insulator layers to bridge the gap, enabling compact transistor spacing without increasing capacitive coupling or shorting risk
4Object-generated harmful factors
If extended metal via is used to connect contact to gate, then capacitance is reduced and cell compactness is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the metal via formation with the existing microprocessor fabrication process steps. The via is formed using the same metal deposition and patterning processes already employed for CPU interconnects, integrating the SRAM-specific via structure into the standard process flow without adding separate manufacturing complexity
Data Source
AI summary
An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.