Compacted Functional Cell Arrays via Next-Generation Lithography
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Solution Overview
Problem
The increase in the number of logic cells in integrated circuit structures, such as FPGAs and SRAM, leads to larger chip sizes and increased costs due to the limitations of conventional 193 nm photolithography, which requires multiple processes, lacks precision, and cannot form dense components or sharp angles.
Innovation Solution
The use of next-generation lithography processes like electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL) to form the boundaries of cells, allowing for higher precision, closer cell spacing, and reduced area requirements, enabling the formation of compacted arrays of functional cells with improved line edge roughness and critical dimension uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional 193 nm photolithography is used to form logic cell boundaries, then the process is well-established and relatively simple, but the manufacturing precision and cell spacing are limited, leading to larger chip area requirements
Solution Approach 1:
The patent transitions from conventional 193 nm photolithography to next-generation lithography (NGL) processes, fundamentally changing the wavelength parameter of the lithography system. This parameter change enables sub-100 nm resolution and allows cell boundaries to be formed closer together, directly reducing the chip area while improving manufacturing precision
Solution Approach 2:
The patent segments the lithography process into distinct stages: forming resist features at sub-100 nm critical dimensions, etching diffusion and gate lines to create cell boundaries, and using multiple patterns to define precise cell edges. This segmentation allows each step to be optimized for precision, enabling tighter cell spacing
2Productivity
If the number of logic cells is increased to meet performance demands, then the processing capability improves, but the required chip area and cost increase
Solution Approach 1:
By changing the lithography wavelength parameter to NGL processes, the patent enables higher cell density without proportionally increasing chip area. The improved resolution allows more cells to be packed into the same area, maintaining productivity growth while controlling area expansion
Solution Approach 2:
The patent utilizes the dimensional space more efficiently by forming cell boundaries in multiple directions and layers. The NGL process enables precise control of cell geometry in both horizontal and vertical dimensions, allowing optimal packing arrangements that maximize cell density without excessive area increase
3Device complexity
If conventional photolithography is used, then the equipment and process are simpler, but multiple masks and processes are required, increasing manufacturing complexity
Solution Approach 1:
The patent merges multiple lithography steps into a unified NGL process flow. By using single-electron-beam direct-write or synchronized multi-beam systems, multiple cell boundary definitions that would require separate masks in conventional lithography are achieved in integrated fashion, reducing overall process complexity while maintaining high precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a 10 to 50 percent reduction in area for the array of functional cells, improved precision, and reduced lithography-induced variations, enabling the formation of dense cell arrays with sub-100 nm resolution without the need for multiple masks or processes.
Implementation Method 1
patterning the resist to form functional cell boundaries using a lithography process that requires one or no masks and is capable of achieving resist features having sub-100 nm critical dimensions, such as electron-beam lithography
Implementation Method 2
patterning the resist to form functional cell boundaries using a lithography process that requires one or no masks and is capable of achieving resist features having sub-100 nm critical dimensions, such as extreme ultraviolet lithography
Implementation Method 3
etching the pattern into the grid-like structure to form the boundaries, such as by ion-beam etching
Data Source
AI summary
Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.