Comparator Calibration in Analog Test Buses for Precise Node Testing
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Solution Overview
Problem
Analog-test-bus apparatuses face inefficiencies due to the risk of accidental shorting and inaccuracies in comparator circuits when testing circuit nodes, particularly due to the use of analog-to-digital converters and the susceptibility to parasitic noise and ground bounce, leading to imprecise measurements and significant IC area usage.
Innovation Solution
The implementation of a digital-to-analog converter (DAC) system that provides a rising or falling reference voltage for comparator circuits to calibrate each circuit node, using sets of calibration data to adjust comparison operations and mitigate inaccuracies, allowing for precise testing of multiple nodes in parallel while minimizing the risk of shorting and noise susceptibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If comparator circuits are made smaller to reduce IC area usage, then area efficiency improves, but measurement precision deteriorates due to imprecision below threshold size
Solution Approach 1:
The patent applies preliminary calibration before actual measurements to compensate for comparator imprecision. Calibration data is obtained by comparing known reference voltages and stored in lookup tables, allowing small comparators to achieve accurate measurements through pre-computed correction values.
Solution Approach 2:
The patent changes the operating parameters of comparators by applying offset voltages through DACs during calibration. By varying reference voltages and measuring comparator responses across multiple parameter points, the system characterizes and compensates for comparator variations, enabling precise measurements despite small comparator sizes.
2Productivity
If multiple circuit nodes are tested in parallel to improve productivity, then testing efficiency improves, but the risk of accidental shorting increases due to supply voltage and ground node connections
Solution Approach 1:
The patent segments the testing process into calibration phase and measurement phase. During calibration, only reference voltages are applied without connecting DUT power/ground nodes. During measurement, nodes are tested sequentially through controlled switching. This segmentation eliminates simultaneous connection risks while maintaining parallel testing capability through multiple comparator circuits.
Solution Approach 2:
The patent introduces controlled switching elements as intermediaries between the test apparatus and DUT nodes. These switches enable selective connection of power and ground nodes only when needed, preventing accidental simultaneous connections. The switching mechanism acts as a mediator that controls node access timing and prevents shorting conditions.
3Adaptability or versatility
If ADCs are used to connect to circuit nodes to enable analog testing, then testing capability improves, but parasitic noise and ground bounce susceptibility increase leading to inaccurate measurements
Solution Approach 1:
The patent replaces the ADC-based measurement mechanism with a comparator-based mechanism. Instead of converting analog voltages to digital values through ADCs, the system uses comparators to directly compare node voltages against reference voltages. This substitution eliminates ADC-related parasitic noise and ground bounce issues while maintaining voltage measurement capability through digital comparator outputs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise and efficient testing of multiple circuit nodes by calibrating comparator circuits using calibration data, reducing the risk of shorting and noise interference, and minimizing IC area usage, thereby improving the accuracy and efficiency of analog-test-bus apparatuses.
Implementation Method 1
analog-test-bus apparatuses and methods thereof involving calibration of comparator circuits for testing circuit nodes... at least one digital-to-analog converter (DAC) that provides a rising or falling reference voltage used to test each of the circuit nodes at one time by comparator circuits comparing the reference voltage against the voltage of the circuit nodes
Data Source
AI summary
An example analog-test-bus (ATB) apparatus includes a plurality of comparator circuits, each having an output port, and a pair of input ports of opposing polarity including an inverting port and a non-inverting port, a plurality of circuit nodes to be selectively connected to the input ports of a first polarity, and at least one digital-to-analog converter (DAC) to drive the input ports of the plurality of comparator circuits. The apparatus further includes data storage and logic circuitry that accounts for inaccuracies attributable to the plurality of comparator circuits by providing, for each comparator circuit, a set of calibration data indicative of the inaccuracies for adjusting comparison operations performed by the plurality of comparator circuits.