Comparator Latch Circuit for Supply-to-Ground Current Cutoff
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Solution Overview
Problem
Comparators in electronics face challenges such as attenuation of accuracy due to offset voltage, kickback noise affecting resolution, and excessive current consumption, particularly in high-speed analog-to-digital converters where supply-to-ground current is a significant issue.
Innovation Solution
A PMOS-based comparator with a preamplifier and latch architecture is enhanced by incorporating a supply-to-ground current prevention signal generator that determines when output nodes reach supply or ground and generates a signal to cut the path for current flow, using circuitry like NAND and NOR gates to prevent current flow when the clock is low.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a preamplifier and latch circuit architecture is used to achieve high speed and accuracy, then measurement precision is improved, but current consumption increases
Solution Approach 1:
The patent applies preliminary action by using a preamplifier stage before the main latch circuit to amplify small differential voltages in advance. This allows the main comparator to operate with smaller signal swings, reducing the current required for high-speed operation while maintaining accuracy. The preamplifier prepares the signal beforehand, enabling the latch to achieve high speed with lower current consumption.
Solution Approach 2:
The patent implements dynamic current consumption by using clock-controlled switches that enable current flow only during the comparison phase. During idle or stable states, the current path is dynamically disconnected, allowing the circuit to maintain high speed performance when needed while minimizing current consumption during steady states. This dynamic operation resolves the contradiction between speed and power by making current consumption time-dependent.
2Productivity
If the comparator operates at high speed to resolve input voltage differences quickly, then productivity is improved, but supply-to-ground current increases
Solution Approach 1:
The patent applies periodic action by using clock signals to periodically enable and disable the comparator operation. The clock-controlled switches allow current to flow only during the active comparison window at each sampling rate cycle, rather than continuously. This periodic operation maintains high productivity by enabling fast comparison when needed while dramatically reducing average supply-to-ground current during the rest of the cycle.
Solution Approach 2:
The patent uses preliminary action by pre-charging capacitive nodes before the comparison phase and preparing the latch circuit in advance. This preliminary preparation allows the comparator to achieve high-speed operation during the brief active window without requiring sustained high current, thereby improving productivity while reducing overall power loss.
3Measurement precision
If PMOS-based architecture is used to reduce flicker noise, then measurement precision is improved, but speed decreases
Solution Approach 1:
The patent merges PMOS and NMOS architectures by using PMOS transistors for the differential input stage where low noise is critical, while employing NMOS transistors in the latch and output stages where high speed is more important. This hybrid approach combines the low flicker noise advantage of PMOS with the high speed advantage of NMOS, resolving the contradiction between noise performance and speed through functional partitioning.
Solution Approach 2:
The patent applies local quality by using PMOS transistors specifically in the noise-critical differential pair region where low flicker noise is essential for measurement precision, while using NMOS transistors in other regions where speed is the priority. This localized application of different transistor types optimizes both noise performance and speed in their respective functional areas.
Data Source
AI summary
An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.