Master-Slave Comparator Circuit With Hysteresis Compensation

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Solution Overview

Problem

Static comparators in high-speed electronics suffer from significant hysteresis, which degrades performance and increases bit error rates, whereas adding a reset phase to compensate for hysteresis in dynamic comparators reduces the effective comparison time.

Innovation Solution

A comparator circuit with a master and slave latch configuration, including a hysteresis compensation circuit that applies predetermined signal level shifts based on the output signal level of the slave latch to minimize the difference between high-to-low and low-to-high thresholds, thereby compensating for hysteresis without requiring a reset phase.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a reset phase is added to compensate for hysteresis in dynamic comparators, then hysteresis is compensated, but the effective comparison time is reduced

Engineering Contradiction:
Improvehysteresis compensationVSAvoideffective comparison time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The hysteresis compensation is performed preliminarily during the comparison phase by adjusting the reference voltage level based on the previous output state, rather than requiring a separate reset phase after comparison. This allows hysteresis compensation to occur in advance, maintaining full comparison time availability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The hysteresis compensation function is merged with the main comparison operation by integrating the compensation mechanism into the existing comparator circuitry, specifically by combining it with the reference voltage generation and the comparison logic, eliminating the need for a separate reset phase.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If hysteresis compensation is implemented in static comparators, then decision robustness is improved, but device complexity increases

Engineering Contradiction:
Improvedecision robustnessVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The hysteresis compensation is achieved through feedback from the comparator output to the reference voltage generation stage. The output state feeds back to adjust the reference voltage level, creating a feedback loop that automatically compensates for hysteresis without requiring additional complex control logic or multiple separate circuits.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The reference voltage generation circuit is given multiple functions: it not only provides the reference voltage for comparison but also implements hysteresis compensation by adjusting its output based on the comparator state. This multi-functionality avoids adding separate dedicated hysteresis compensation circuitry, thereby limiting complexity increase.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10530346B2Comparator circuit
Publication Date: 2020.01.07 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • US10530346B2 patent drawing
  • US10530346B2 patent drawing
  • US10530346B2 patent drawing

AI summary

An aspect of the disclosure includes a comparator circuit comprising: a master latch comprising a first amplifier circuit and a first latch circuit coupled to an output of the first amplifier circuit; a slave latch comprising a second amplifier circuit having an input coupled to the output of the first amplifier circuit, and a second latch circuit coupled to an output of the second amplifier circuit; and a hysteresis compensation circuit coupled to the output of the second amplifier circuit and configured to cause a first predetermined signal level shift of an output signal of the first amplifier circuit in response to a high signal level at the output of the second amplifier circuit, and configured to cause a second predetermined signal level shift of an output signal of the first amplifier circuit in response to a low signal level at the output of the second amplifier circuit.