Pulse Generation By Differential Amplifiers TRIZ Cases

A controllable buffer chain replaces voltage-to-current conversion to generate stable low-noise current ramps despite PVT variation.

Trimmed impedance networks at comparator inputs improve common-mode behavior and stabilize oscillator frequency across PVT changes.

Dual triangle or sawtooth carriers let PWM switch amplitude and frequency by load, cutting ripple current, conduction loss, and idle power.

Switch-controlled feedback around pregain stages cancels comparator offset errors and improves SAR ADC precision under process variation.

A slave-latch-driven level shift compensates static comparator hysteresis without a reset phase, preserving comparison time and reducing jitter.

Series differential amplifiers and an auxiliary start circuit cut power supply noise sensitivity, reduce jitter, and widen oscillator frequency range.

Programmable resistors and reference voltages set pulse width precisely from one ramp signal, avoiding complex timing redesign for short pulses.

A charge-discharge control unit speeds Miller and gate capacitance switching so comparator oscillators can track high-frequency control signals.

Dual current mirrors and an SR latch control two capacitors to deliver stable high-frequency oscillation with low power and low deviation.

Synchronized comparator pulses maintain L-C oscillation in HDX passive RFID tags without frequency drift, reducing power use and extending range.

Output-state feedback shifts comparator thresholds to cut hysteresis and jitter without adding a reset phase or reducing comparison time.

Comparator feedback adjusts the sawtooth ramp level to keep peak voltage within reference bounds despite process, supply, temperature, and aging shifts.

Alternating comparator inputs each clock cycle cancels offset drift in an on-chip RC oscillator, stabilizing frequency without a crystal.

Selective SEU hardening in the slave latch and an added inverter reduce DFF FIT mismatch while preserving a simpler master latch.