Comparator Impedance Trimming for PVT-Stable Oscillators
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Solution Overview
Problem
Conventional oscillators suffer from significant frequency variations due to process, voltage, and temperature changes, which conventional trimming techniques fail to adequately address, especially in relaxation oscillators with non-ideal comparators and clock buffers.
Innovation Solution
Incorporating first and second impedance networks with trim elements, such as capacitors and trim resistors, in the input terminals of first and second comparators, and utilizing a current mirror circuit to generate bias signals, improves common mode variation and frequency stability across a wide range of process-voltage-temperature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional trimming techniques are used to adjust reference resistor, then frequency stability is partially improved, but common mode voltage variations across wide PVT remain insufficiently reduced
Solution Approach 1:
The patent divides the single reference resistor trimming approach into separate trimming for the first and second impedance networks. This segmentation allows independent optimization of common mode voltage for each comparator path, effectively reducing PVT variations that a single trimming point cannot address.
Solution Approach 2:
The patent applies different impedance values to the first and second impedance networks connected to the non-inverting inputs of the comparators. This local quality adjustment compensates for asymmetric PVT effects on each comparator, improving common mode rejection locally at each comparator input rather than using a global trimming approach.
2Power
If relaxation oscillators with non-ideal comparators are used, then low voltage and low power operation is achieved, but frequency variations due to temperature and supply voltage increase
Solution Approach 1:
The patent applies preliminary compensation by adding trim elements to the impedance networks before the oscillator operates under PVT variations. This preliminary adjustment pre-compensates for expected temperature and voltage drifts, allowing the low-power relaxation oscillator to maintain frequency stability without requiring complex real-time correction circuits.
Solution Approach 2:
The patent changes the impedance parameters (resistance and capacitance values) of the first and second impedance networks to optimize the common mode voltage at comparator inputs. By carefully selecting these parameters, the oscillator achieves low power consumption while compensating for temperature and supply voltage effects on frequency stability.
Data Source
AI summary
An oscillator includes first and second comparators, a first impedance network having a first trim element therein, and a second impedance network having a second trim element therein. The first impedance network is electrically connected to a first input terminal of the first comparator, and the second impedance network is electrically connected to a first input terminal of the second comparator. The first and second impedance networks are configured to cause an improvement in common mode variation within the first and second comparators, in response to trimming of at least one of the first and second trim elements.