Comparator Hysteresis Circuit With Delayed Differential Pair Switching
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Solution Overview
Problem
Comparator circuits often experience output transient glitches due to noise-induced switching when comparing analog input signals with close voltage levels, and existing hysteresis methods can be inaccurate, leading to varying voltage thresholds and timing mismatches that cause parasitic capacitor charging currents.
Innovation Solution
The comparator circuit incorporates a timing circuit with delay elements to control the enable timing of differential pairs, ensuring that the signal in the longer path reaches the output node no later than the signal in the shorter path, thereby preventing transient glitches by introducing time domain hysteresis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hysteresis is applied to prevent noise-induced switching, then output stability is improved, but voltage threshold accuracy deteriorates due to timing mismatches
Solution Approach 1:
The patent applies preliminary action by pre-charging parasitic capacitors through controlled current paths before the comparator output switches. Timing circuits activate specific transistors in advance to charge capacitors C1 and C2 through designated paths, ensuring that when switching occurs, the capacitors are already prepared with appropriate voltage levels. This prevents transient glitches and maintains accurate hysteresis thresholds.
Solution Approach 2:
The patent introduces intermediary elements including timing circuits and controlled current sources that mediate between the comparator output and the differential pairs. These intermediaries precisely control the charging and discharging of parasitic capacitors, ensuring that hysteresis voltages are applied at the correct moments without causing timing mismatches or threshold inaccuracies.
2Reliability
If differential pairs are switched based on comparator output transition, then hysteresis function is achieved, but transient glitches are generated due to timing mismatches
Solution Approach 1:
The timing circuits perform preliminary actions by activating transistors Q1-Q4 in a specific sequence before the comparator output switches. This ensures that parasitic capacitors are charged or discharged through controlled paths ahead of time, preventing transient glitches when the differential pairs switch states.
Solution Approach 2:
The patent converts the potentially harmful effect of parasitic capacitors into a beneficial mechanism. Instead of allowing uncontrolled charging/discharging that causes glitches, the timing circuits exploit these capacitors to provide controlled hysteresis voltage adjustments, transforming the harmful timing mismatches into useful hysteresis functionality.
3Reliability
If individual trip thresholds are applied based on output state, then noise-induced switching is reduced, but circuit complexity increases
Solution Approach 1:
The timing circuits perform multiple functions simultaneously: they control the switching of differential pairs, charge/discharge parasitic capacitors, generate hysteresis voltages, and synchronize state transitions. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall circuit complexity while maintaining noise rejection capabilities.
Data Source
AI summary
A comparator circuit includes a first transistor, a second transistor, a first switch, a second switch, and a timing circuit. The first transistor and the second transistor are coupled as a differential pair and are configured to compare an input signal to a hysteresis voltage. The first switch is coupled to the first transistor and is configured to selectably enable the first transistor. The second switch is coupled to the second transistor and is configured to selectably enable the second transistor. The timing circuit is coupled to the first switch and the second switch and is configured to close the first switch responsive to a signal transition at an output of the comparator circuit and close the second switch a predetermined delay time after the first switch is closed.