Gate Charge Profiling Using Comparator Timing for Power Transistors

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Solution Overview

Problem

Power electronics systems face challenges in optimizing switching performance and reducing switching losses due to variations in gate charge characteristics of power transistors, which are influenced by parasitic elements and design margins, leading to inefficiencies and increased electromagnetic interference (EMI).

Innovation Solution

A gate charge profiler system that includes a voltage comparator and timer unit to determine the gate charge of power transistors by measuring the time value of the gate drive current and input signal transitions, allowing for precise calibration of gate drive currents and time intervals to optimize switching performance and reduce design margins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If gate drive current is increased to improve switching speed, then switching performance is improved, but switching losses and EMI increase

Engineering Contradiction:
Improveswitching speedVSAvoidswitching losses
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The gate driver circuit dynamically adjusts the gate drive current based on real-time gate charge characteristics of the power transistor. The system measures actual gate charge values and modifies the drive current waveform accordingly, transitioning from static to dynamic control to optimize switching performance while minimizing losses

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the gate drive current parameters (amplitude, duration, waveform shape) based on measured gate charge characteristics. By adapting current parameters to match actual transistor behavior, the system achieves optimal switching speed while reducing excessive current that causes losses and EMI

Inventive Principle:
Principle #35Parameter changes

2Reliability

If design margins are increased to account for gate charge variations, then reliability is improved, but efficiency decreases due to increased EMI and switching losses

Engineering Contradiction:
Improveswitching reliabilityVSAvoidswitching losses
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The system implements feedback by measuring actual gate charge characteristics and using this information to adjust gate drive parameters. This closed-loop approach replaces conservative design margins with real-time adaptive control, maintaining reliability while eliminating the efficiency penalties associated with oversized design margins

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs self-characterization by automatically measuring its own gate charge parameters and using this self-knowledge to optimize its operation. This self-adjusting capability eliminates the need for external calibration or conservative design margins, improving efficiency while maintaining reliability

Inventive Principle:
Principle #25Self-service

3Device complexity

If gate charge characteristics are not accurately determined, then device complexity is reduced, but switching performance optimization is limited

Engineering Contradiction:
Improvemeasurement circuit complexityVSAvoidswitching efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The system uses an intermediary measurement approach, employing a comparator and timer to indirectly measure gate charge characteristics through voltage threshold comparisons. This intermediary method achieves accurate gate charge determination without requiring complex direct measurement circuits, balancing simplicity with performance optimization

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4312369A1Gate charge profiler for power transistors
Publication Date: 2024.01.31 INFINEON TECH AUSTRIA AG
  • EP4312369A1 patent drawingFigure 1
  • EP4312369A1 patent drawingFigure 2A
  • EP4312369A1 patent drawingFigure 2B

AI summary

A gate charge profiler (102) for a power transistor (Qpwr) may include a voltage comparator unit (120) and a timer unit (130). An input signal (Sig) may control a gate drive current input (Ig_drive) to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage (Vds, Vgs) and a threshold voltage (Vth), and to output a comparison signal (CS). The input voltage may be a drain-source voltage (Vds) across the drain and the source of the power transistor or a gate-source voltage (Vgs) across the gate and the source of the power transistor. The timer unit may be configured to output a time value (T_VAL) based on input of a transition of the input signal (Sig) and input of the comparison signal (CS). Based on this determined time value determined by the gate charge profiler and the gate drive current, a gate charge can be calculated by a controller.