Compiler-Driven FPGA Virtualization for Multitenancy
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Solution Overview
Problem
Current technologies lack a standard method for virtualizing field programmable gate arrays (FPGAs) in data centers, particularly for workload migration and multitenancy, due to the distributed nature of FPGA state and the absence of a widely accepted approach for sharing or relocating FPGA programs.
Innovation Solution
A compiler-driven strategy for FPGA virtualization using a combined compiler/runtime environment, such as Cascade, which transforms HDL descriptions to support sub-clock-tick granularity and enables workload migration and multitenancy by managing the FPGA state and interleaving asynchronous data and control requests between instances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a general strategy for virtualizing programmable devices is implemented, then multitenancy and workload migration are enabled, but the distributed nature of FPGA state and absence of standard approaches increases system complexity
Solution Approach 1:
The patent introduces a compiler-driven virtualization layer as an intermediary between the FPGA hardware and multiple tenants/workloads. This compiler translates high-level HDL descriptions into intermediate representations that can be efficiently mapped to the underlying programmable device, abstracting away the complexity of state management and resource allocation. The compiler acts as a mediator that handles the distributed nature of FPGA state automatically, enabling multitenancy and workload migration without requiring complex manual management of the underlying hardware complexity.
2Ease of manufacture
If hardware accelerators are virtualized without hardware-specific modifications, then ease of deployment is improved, but managing FPGA state and interleaving asynchronous requests increases complexity
Solution Approach 1:
The patent replaces traditional hardware-based state management mechanisms with a compiler-driven software approach. Instead of modifying the FPGA hardware to include virtualization-specific circuitry or state management logic, the invention uses a compiler that translates HDL descriptions into forms suitable for virtualized execution. This substitution of mechanical (hardware) approaches with software-based compilation and translation enables easier deployment across different hardware platforms while the compiler automatically handles the complexity of state management and asynchronous request interleaving.
3Productivity
If multiple sub-programs are combined into a monolithic program, then resource utilization is improved, but compilation and loading time increases
Solution Approach 1:
The patent applies preliminary action by pre-compiling individual sub-programs into intermediate representations before they are combined into a monolithic program. The compiler processes each sub-program separately in advance, generating optimized intermediate code that can be efficiently merged. This preliminary compilation step allows the system to maintain high resource utilization through monolithic program execution while reducing the overall compilation and loading time, as the individual components are already prepared and optimized before integration.
Data Source
AI summary
Examples provide a method of virtualizing a hardware accelerator in a virtualized computing system. The virtualized computing system includes a hypervisor supporting execution of a plurality of virtual machines (VMs). The method includes: receiving a plurality of sub-programs at a compiler in the hypervisor from a plurality of compilers in the respective plurality of VMs, each of the sub-programs including a hardware-description language (HDL) description; combining, at the compiler in the hypervisor, the plurality of sub-programs into a monolithic program; generating, by the compiler in the hypervisor, a circuit implementation for the monolithic program, the circuit implementation including a plurality of sub-circuits for the respective plurality of sub-programs; and loading, by the compiler in the hypervisor, the circuit implementation to a programmable device of the hardware accelerator.