Computer Aided Design TRIZ Cases
- Static COI Analysis for IC Diagnostic Coverage
A static cone of influence analysis generates fault lists from gate-level netlists to enable register-transfer level simulation.
- Parallel Flip-Flop Timing Analysis Using Quadsection Search
A quadsection analysis method divides search windows into four sections to perform parallel timing simulations for flip-flop cells.
- Hierarchical Macro Placement for IC Layout Area Optimization
Dividing macros into hierarchical groups with dynamic channel widths reduces routing congestion and manufacturing costs.
- Compiler-Driven FPGA Virtualization for Multitenancy
A hypervisor compiler merges sub-programs into monolithic circuits to virtualize FPGAs across multiple tenants.
- Traffic Predictor for UVM Register Abstraction Layer Verification
A traffic predictor monitors data traffic over communication interfaces to generate expected responses for circuit design verification.
- Automated HBM Channel Identification for 3DIC Auto-Routing
An automated system identifies high-bandwidth memory channels by analyzing candidate nets and bump patterns to generate subchannels.
- Waveform Invariant Node Decomposition for Compact Timing Models
Decomposing circuit paths at waveform invariant nodes reduces model size and computational complexity.